Every FPGA chip, or FPGA, is composed of a finite number of predefined resources with programmable interconnects. These interconnects implement the digital circuit you design with the LabVIEW FPGA Module. When you create an FPGA VI, you design a circuit schematic that describes how logic blocks are wired together on the FPGA. When you compile the VI, the LabVIEW FPGA Compile Server translates the FPGA VI into the FPGA circuit.
|Note This topic contains low-level FPGA implementation concepts. You do not need to understand these concepts to get started with the LabVIEW FPGA Module, but understanding them can help you build more efficient FPGA VIs.|
The following illustration shows the relationship between logic blocks, I/O blocks, and programmable routing on an FPGA.
The following FPGA specifications are important to consider when designing an FPGA application.
Refer to the NI Developer Zone for more information about the fundamental parts of the FPGA.
Configurable logic blocks are made of flip-flops and look-up tables (LUTs). A flip-flop is a circuit capable of two stable states and represents a single bit. A LUT is a logic block that stores a predefined list of outputs for every combination of inputs, thereby providing a fast way to retrieve the logic operation output. LUTs have different numbers of inputs, commonly two to six, depending on the FPGA. A slice contains a set number of LUTs and flip-flops, which also varies depending on the FPGA. For example, a slice on a Virtex-II FPGA has two LUTs and two flip-flops. A slice on a Virtex-5 FPGA has four LUTs and four flip-flops.
A register is a group of flip-flops that stores a bit pattern. A register on the FPGA has a clock input, input data, and output data. Every clock cycle, the input data is latched, stored internally, and the output data is updated to match the internally stored data. FPGA VIs use registers to perform the following functions:
Registers are a key concept in understanding timing considerations for FPGA VIs.
Block RAM, or block memory, is RAM that is embedded throughout the FPGA for storing data. In general, LabVIEW uses block RAM when synthesizing Memory and FIFO functions. You can specify how LabVIEW implements FIFOs and memory items using the FIFO Properties and Memory Properties dialog boxes, respectively.