You can use the single-cycle Timed Loop in FPGA VIs to optimize your code, implement multiple clock domains, and execute code in one clock cycle of the default FPGA target clock or at a rate you specify.
When you place code inside a single-cycle Timed Loop, LabVIEW does not place additional registers in the compiled function code. This increases the combinatorial path length of the code and may cause timing violation errors when you compile the FPGA VI.
|Note LabVIEW cannot remove internal registers from functions such as the Memory Method Node and FFT Express VI.|
As the longest path through the logic inside the single-cycle Timed Loop increases, the maximum clock rate decreases. You can pipeline long combinatorial paths to keep the final maximum clock rate high. You also can separate sections of independent logic into different clock domains. You then can use long combinatorial paths in a slow clock domain and short combinatorial paths in a fast clock domain.