Unsupported LabVIEW Features (FPGA Module)

In addition to providing I/O capabilities, the FPGA Module enables you to use the LabVIEW VIs and functions appropriate for FPGA targets.

Restricted and Unavailable VIs and Functions

Some LabVIEW VIs and functions are not available or have restrictions in FPGA VIs.

The following LabVIEW features are not available for FPGA VIs:

• ActiveX
• Dialog boxes
• File I/O
• Floating-point functions
• For Loop iteration parallelism
• Math and Signal Processing VIs not specific to the FPGA Module
• Printing
• Programmatic menus
• Shared variables (except some targets that support the NI Scan Engine)
• Variable-size and multi-dimensional arrays
• VI Server
• VI Server properties and methods

Support for other LabVIEW features varies by target.

Floating-Point Operations

You cannot use floating-point operations in FPGA VIs. Instead, you can use integer numeric and fixed-point data types. You can perform integer and fixed-point math by using the Numeric functions. You also can perform more advanced integer math, analysis, and control operations using the FPGA Math & Analysis VIs.

Note  The FPGA Module also provides the High Throughput Math functions for fixed-point math and analysis on FPGA targets. These functions are different from the Numeric functions.

When you perform integer math, the results can overflow. Integer overflow occurs when the result of a mathematical operation exceeds the range of the output data type. For example, the range of a U8 integer is 0 to 255. Adding two U8 integers together that have a result greater than 255 results in overflow, such as 200 + 70. When overflow occurs, the result rolls over, or wraps, at the limit of the range and the result modulo 256 is returned. For example, a result of 270 for a U8 integer wraps at 256 and returns 14.

You can take advantage of the rollover behavior that occurs with overflow in some applications. For example, the execution time measurement example relies on the rollover behavior of overflow for proper operation. The example configures the Tick Count Express VIs with an 8-bit Size of Internal Counter and milliseconds for Counter Units. When the internal counter of the Tick Count Express VI reaches 255 ms, it rolls over to 0. If the first Tick Count Express VI returns a Tick Count of 132 ms and the execution time of the LabVIEW code to be measured takes 140 ms, the internal counter has rolled over and the second Tick Count Express VI returns a Tick Count value of 16 ms. When the block diagram subtracts 132 from 16, overflow occurs and results in the value of 140.

Note  The Tick Count Express VI takes a single cycle to execute. In this example, if you set Counter Units as Ticks instead of mSec, the returned result from the subtraction is 141 even though the LabVIEW code in the middle sequence takes only 140 ticks to execute.

If you want to avoid integer overflow, you can use the following techniques:

• Convert integers to the fixed-point data type using the To Fixed-Point function.
• Use a larger output data type. If you use a larger output data type, you take up more space on the FPGA target but you can program the FPGA VI more quickly and easily and receive more accurate data.
• Use the Scale By Power Of 2 function to reduce the magnitude of the inputs. If you use the Scale By Power Of 2 function with a constant, you minimize the amount of space you use on the FPGA target to handle saturation. However, you lose precision and you also must carefully program the FPGA VI to be sure you scale all inputs and outputs correctly.

Multi-Dimensional, Bounded, or Variable-Size Arrays

You cannot use multi-dimensional, bounded, or variable-size arrays in FPGA VIs. You can use only fixed-size, one-dimensional arrays in FPGA VIs. You can make any array constant, control, or indicator fixed-size by right-clicking the array index and selecting Set Dimension Size from the shortcut menu.

You cannot use an array function that returns a variable-size array. However, if you use appropriate constants with many array functions, the resulting array is fixed-size. For example, if you use the Array Subset function, you must wire constants to the index and length parameters so that the resulting subarray is fixed-size.

Tip  Arrays consume significant space on the FPGA. To optimize the FPGA VI, avoid using arrays larger than 512 bits.

Shared Variables and the NI Scan Engine

Support for shared variables varies by FPGA target and RT controller. Not all CompactRIO RT controllers support the NI Scan Engine. Refer to the specific FPGA target or RT controller hardware documentation for more information about FPGA target and RT controller functionality.