Placing the High Throughput Math Functions in a Single-Cycle Timed Loop (FPGA Module)

You can place all High Throughput Math functions inside a single-cycle Timed Loop. However, be aware of the following caveats in this situation:

• Most High Throughput Math functions are multi-cycle, which means these functions take more than one cycle to return a valid result. If you place a multi-cycle High Throughput Math function inside a single-cycle Timed Loop, this function does not return a valid value during every clock cycle. The throughput rate of the function and the values of the handshaking terminals determine the clock cycles during which this function produces a valid value.
• If you place several High Throughput Math functions inside a single-cycle Timed Loop, the combinatorial path might become too long and cause timing violations when you compile the FPGA VI. For this reason, the High Throughput Math functions provide ways to reduce the length of the combinatorial path.

Single-Cycle vs. Multi-Cycle Functions

The High Throughput Add, Subtract, and To Fixed-Point functions are single-cycle functions. These functions execute in a single FPGA clock cycle. All other High Throughput Math functions are multi-cycle functions. These functions need more than one clock cycle to execute. If you place several multi-cycle functions in a single-cycle Timed Loop, the combinatorial path might become too long to execute in a single clock cycle.

Achieving a High Throughput Rate

For a multi-cycle High Throughput Math function in a single-cycle Timed Loop, you use the Throughput control, located in the configuration dialog box of that function, to specify the throughput rate you want the function to achieve. The throughput rate, in cycles/sample, is the minimum number of FPGA clock cycles that must elapse before this function can receive valid input data. Therefore, smaller values of the Throughput control mean the function can execute faster, because fewer clock cycles must elapse before the function is ready to receive valid input data.

Note  The Throughput value of a single-cycle function always is 1 cycle / sample.

To demonstrate the importance of the Throughput control, consider three multi-cycle High Throughput Math functions connected by handshaking terminals. Within this series of three connected functions, the slowest throughput rate in that series (that is, the Throughput control with the highest value) is the fastest throughput rate that all connected functions can achieve. This limitation is true for each independent series of connected functions in a single-cycle Timed Loop.

Note  The Throughput control of a function is available only if you place that function inside a single-cycle Timed Loop. If you place the function outside a single-cycle Timed Loop, LabVIEW dims the Throughput control and displays a constant value of 1 call / sample . This value means the function can receive valid input data every time the VI calls the function.

Handshaking

Although multi-cycle High Throughput Math functions execute during every clock cycle of a single-cycle Timed Loop, these functions do not return valid values during every cycle. You can configure these functions to display four handshaking terminals on the function icon. You use these terminals to determine when the following actions occur:

• The function discards data from upstream functions.
• The function accepts data from upstream functions.
• Downstream functions discard data from the function.
• Downstream functions accept data from the function.

Note  Different functions have different criteria for determining whether the handshaking terminals appear. For example, the terminals appear on the High Throughput Divide icon when you select Inside single-cycle Timed Loop. To enable these terminals on the High Throughput Add function, you also must place a checkmark in the Register outputs checkbox.

Reducing the Length of the Combinatorial Path

If you place several High Throughput Math functions inside a single-cycle Timed Loop, the combinatorial path can become too long to achieve the necessary clock rate. In this situation, the Compilation Status window returns an error when you compile the FPGA VI. LabVIEW helps avoid these errors by pipelining the functions automatically. You also can avoid these errors by adding input and/or output registers to the function.

Automatic Pipelining

If you place a High Throughput Math function inside a single-cycle Timed Loop and specify a small Throughput value to achieve a high throughput rate, LabVIEW might pipeline the function internally. LabVIEW bases the amount of pipelining on the options, such as the word length of the output data type, you specify in the configuration dialog box. Pipelining reduces the length of the combinatorial path and increases the chance that the function can achieve the specified clock rate. You can see whether LabVIEW is pipelining a function by looking at the Configuration Feedback section of a configuration dialog box.

Note  Because of the nature of multipliers on an FPGA chip, the High Throughput Multiply function gives you more detailed control over when and how LabVIEW pipelines this function.

Adding Input and Output Registers

You also can reduce the length of the combinatorial path by adding registers for the inputs and/or outputs of a function. Adding registers can prevent compilation errors. However, each set of registers also increases the latency of the function by one cycle, which means you must wait an extra cycle to receive a valid output value.

Note  Some functions, such as the High Throughput Subtract function, support adding only one set of registers.

The following figure shows how data flows through a function that contains these internal registers.

Use the Registers section of a configuration dialog box to add input and/or output registers.

Note  If you place a function outside a single-cycle Timed Loop, LabVIEW automatically places registers at the function outputs when you compile the VI.