You can specify clock domains in FPGA VIs using the single-cycle Timed Loop. All available FPGA target clocks appear in the Project Explorer window as FPGA target base or derived clocks. You can select any FPGA target base or derived clock that the FPGA target supports as the clock for a single-cycle Timed Loop. However, the combinatorial path length of the code you place in the single-cycle Timed Loop must be short enough to execute at the clock rate you specify.
You might need to transfer data between single-cycle Timed Loops set to run under different clock domains. Digital inputs on most FPGA targets are asynchronous to the top-level FPGA target clock and must be resynchronized. Some FPGA targets allow you to use external clocks or I/O resources specially synchronized to an onboard clock. If input data is already synchronous to the top-level FPGA target clock, you can avoid the resynchronization overhead. Refer to the specific FPGA target hardware documentation for information about the synchronicity of available I/O resources.
To transfer data between clock domains, you can use local or global variables, Block Memory FIFOs, or single-cycle Timed Loop tunnels. The following table summarizes the characteristics of each method.
|Transfer Method||FPGA Resource||Lossy?||Between Parallel Loops?||Between Unlimited Domains?||Common Use|
|Local and Global Variables||Logic||Yes, unless implemented with handshaking||Yes||Yes||Control, Simulation|
|Block Memory FIFOs||Logic and Memory||No||Yes||No||Datalogging|
|Single-Cycle Timed Loop Tunnels||Logic||No||No||No||Datalogging|
You can write to a local or global variable from a maximum of one clock domain. You then can read from the local or global variable in as many clock domains as you need. LabVIEW transfers data from the writing domain to the reading domains and uses handshaking to maintain data integrity. You must wait several clock cycles of both the source and destination to handshake a new value. Some values you write from one clock domain might not be read by the destination domain because of the handshaking overhead.
|Note The data for each control handshakes separately. To ensure that all data written in the same iteration of the sending clock domain arrive together in the destination clock domain, place data in a cluster.|
You can use a target-scoped or VI-defined FIFO to transfer data between clock domains only if you choose Block Memory as the Implementation of the FIFO in the General FIFO Properties page. You can write data to a Block Memory FIFO from a maximum of one clock domain. You then can read the FIFO from a maximum of one other clock domain.
|Note If you use Block Memory FIFOs and the clock that the FIFO is using stops, the clock domain receiving the data needs one additional write clock cycle to be aware of the last data point written.|
You can use the single-cycle Timed Loop tunnel to wire input and output signals on a single-cycle Timed Loop. LabVIEW handshakes input signals to the loop clock domain. After each iteration of the single-cycle Timed Loop terminates, LabVIEW handshakes any output signals to the top-level FPGA target clock. Single-cycle Timed Loop tunnels maintain the LabVIEW dataflow and therefore cannot be used to transfer data among parallel loops.
|Note LabVIEW returns the Code Generation Errors window if you try to transfer data among multiple clock domains without using one of the above methods.|