To transfer data between an FPGA VI and a Windows-based host VI programmatically, you can use either programmatic front panel communication or Direct Memory Access (DMA). These methods have a user-defined timing model, which means you must create block diagram code that synchronizes the FPGA VI with the host VI.
If the host VI is a VI running on a real-time (RT) controller and the FPGA target supports the NI Scan Engine, you can use user-defined I/O variables to transfer data between the FPGA VI and the RT host VI. This method uses the NI Scan Engine as the timing model.
The following table summarizes the characteristics of these methods.
|Data Transfer Method||Throughput Rate||Call Overhead||Host CPU Usage||Timing Model||Common Use|
|Programmatic Front Panel Communication||Lower||Lower||Higher||User-Defined||Control, Simulation|
|Direct Memory Access||Higher||Higher||Lower||User-Defined||Datalogging, Acquiring or generating waveforms|
|User-Defined I/O Variables (RT host VI only)||Lower||Lower||Lower||NI Scan Engine||Applications that need to transfer coherent sets of data|
Use programmatic front panel communication for small, frequent data transfers and DMA for streaming large amounts of data at a time. Use user-defined I/O variables for transferring coherent sets of FPGA I/O data to and from an RT host VI. If you are not sure which data transfer method to use, try using programmatic front panel communication first. If you find that programmatic front panel communication cannot meet the throughput requirements, try another method.
When you need to transfer single data points as quickly as possible, such as when transferring data for control or simulation purposes, you can use the Read/Write Control function in the host VI to access the front panel controls and indicators of the FPGA VI, as shown in the following block diagram.
|Note Support for programmatic front panel communication varies by FPGA target. Refer to the specific FPGA target hardware documentation for more information.|
An advantage of programmatic front panel communication relative to DMA is its low call overhead. Although you cannot attain high throughput with programmatic front panel communication, each call to the Read/Write Control function initiates data transfer with minimal delay. Therefore, programmatic front panel communication is ideal for small, frequent data transfers.
When you do not need to transfer each data point immediately, such as when transferring data from the FPGA to the host computer for datalogging purposes, you can wait for a large amount of data to accumulate and use a DMA FIFO to transfer the data efficiently.
|Note Support of DMA FIFOs varies by FPGA target. Refer to the specific FPGA target hardware documentation for more information.|
An advantage of DMA is that the host computer processor can perform calculations while the FPGA target transfers data to the host computer memory. LabVIEW performs DMA transfers through bus mastering. FPGA targets that support DMA FIFOs can master the PCI bus to directly access memory on the host computer without involving the host computer processor.
A disadvantage of DMA FIFOs is the overhead associated with each data transfer. It takes longer to initiate a data transfer using the DMA FIFO than it does using the Read/Write Control function. Therefore, DMA FIFOs make more sense for transferring large amounts of data at a time.
A DMA FIFO allocates memory on both the host computer and the FPGA target, yet acts as a single FIFO. The FPGA VI writes to the FIFO one element at a time with the Write method of the FIFO Method Node or reads from the FIFO one element at a time with the Read method. The host VI reads from or writes to the FIFO one or more elements at a time with the Invoke Method function.
LabVIEW uses a DMA Engine to transfer DMA FIFO data between the FPGA and the host computer. The DMA Engine includes driver software and hardware logic. When the DMA Engine runs, it automatically transfers data between the DMA FIFO memory on the FPGA and the DMA FIFO memory on the host computer so they act as one FIFO array.
When you create a DMA FIFO, you specify the size, or depth, of the FIFO buffer on the FPGA. You also can specify the size of the FIFO buffer on the host computer by using the Invoke Method function in a host VI to invoke the Configure method. If you do not specify the size of the host memory part of the FIFO, the Invoke Method function uses a default of 10,000 elements. Make sure the host and FPGA parts of the FIFO are large enough so that they do not fill in the case of the longest expected delay in the host VI. For example, PCI bus traffic can cause delays in automatic transfers from the FPGA target to the host. The purpose of a FIFO buffer is to accommodate jitter, so the longer the delays you expect, the more depth you need.
Consider the following situations when you specify the depth of the DMA FIFO:
If you use programmatic front panel communication or DMA FIFOs to transfer coherent sets of FPGA I/O data to an RT host VI, you must create block diagram code that synchronizes the FPGA VI with the host VI. If the FPGA target supports the NI Scan Engine, you can use the NI Scan Engine to synchronize this data transfer. You then can use user-defined I/O variables to transfer data between the FPGA VI and the RT host VI.
|Note An I/O variable is a type of shared variable that uses the NI Scan Engine for single-point access to I/O data. Refer to the specific FPGA target hardware documentation for information about support for the NI Scan Engine.|
Using the NI Scan Engine reduces the amount of code you have to create to access and transfer coherent sets of data between FPGA I/O channels and the RT host VI. With user-defined I/O variables, you can process data on the FPGA target before sending that data to the RT host VI and after sending that data back to the FPGA VI. For example, you can create an application that executes the following steps:
Steps 2 and 3 involve user-defined I/O variables to transfer data between the FPGA VI and RT VI.
Right-click the chassis item in the Project Explorer window and select New»User-Defined Variable from the shortcut menu to create a new I/O variable. Because all I/O variables are unidirectional, you must configure the direction of each user-defined I/O variable as either FPGA to Host or Host to FPGA.
I/O variables that you create this way appear in a container labeled User-defined Variables.
|Note A chassis item can include only one user-defined I/O variable container. However, a user-defined I/O variable container can contain multiple user-defined I/O variables.|
Be aware of the following caveats when creating and using user-defined I/O variables:
User-defined I/O variables rely on timing information from the NI Scan Engine. You can access this timing information by adding the Scan Clock I/O item to the block diagram of the FPGA VI. This I/O item transmits timing information, such as the number of FPGA clock cycles during which the signal is high, from the Scan Engine to the FPGA VI. Use this timing information to design an application that guarantees coherency of the data sets you transfer between the FPGA VI and the RT host VI.
Not all chassis support the Scan Clock I/O item. If you are using a chassis that does support this item, the item is located in the Project Explorer window under the Chassis I/O item for the FPGA Target. The following figure shows the location of this item.