Using SubVIs on the FPGA (FPGA Module)
LabVIEW allows you to encapsulate common sections of code as subVIs to facilitate their reuse on the block diagram. While you can run only one top-level FPGA VI, you can use multiple VIs on the FPGA by placing subVIs on the block diagram of the top-level FPGA VI.
Reentrant and Nonreentrant SubVIs
You can configure a subVI as a single instance shared among multiple callers, also known as a non-reentrant subVI. You also can configure a subVI as reentrant to allow parallel execution. By default, VIs created under an FPGA target are reentrant. To make a subVI non-reentrant, select Execution from the Category pull-down menu of the VI Properties dialog box and remove the checkmark from the Reentrant execution checkbox.
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Caution VIs not created under an FPGA target or created using the FPGA Module 8.2.x or earlier are non-reentrant by default. Moving or copying VIs to or from an FPGA target does not change the reentrancy setting of the VI. |
If you use a non-reentrant subVI in an FPGA VI, only a single copy of the subVI becomes hardware and all callers share the hardware resource. If you use a reentrant subVI in an FPGA VI, each instance of the subVI on the block diagram becomes a separate hardware resource. For example, if you have five instances of an event counter configured as a reentrant subVI on the block diagram, LabVIEW implements five independent copies of the event counter hardware on the FPGA.
In general, configuring a subVI as reentrant improves speed because instances of the subVI execute in parallel. On the other hand, configuring a subVI as non-reentrant generally saves space because each instance of the subVI shares the same FPGA hardware. However, when you use multiple instances of a non-reentrant subVI, extra FPGA resources are used for arbitration. In some cases, the arbitration resources can cause a non-reentrant configuration to consume as much or more space on the FPGA as a reentrant configuration.
The following table summarizes the typical advantages and disadvantages of non-reentrant and reentrant subVIs.
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Note When possible, avoid shared resources in reentrant subVIs. If you use a shared resource in a reentrant subVI, each instance of the subVI must use arbitration to access the shared resource, which can impede parallel execution. |
| VI Type | FPGA Speed | FPGA Utilization |
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Reentrant |
Higher—Multiple calls to the same subVI run in parallel. |
Can be higher because each instance of the subVI on the block diagram uses space on the FPGA. However, reentrant subVIs do not use FPGA resources for arbitration. |
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Non-reentrant |
Lower—Each call to the subVI waits until the previous call ends. |
Can be lower because only one instance of the subVI exists on the FPGA no matter how many times you use it. However, non-reentrant subVIs use FPGA resources for arbitration. |
Specifying FPGA I/O Items When Calling SubVIs
Use the FPGA I/O control, located on the Modern»Name Controls palette, to pass FPGA I/O items to the block diagram. You can use FPGA I/O controls to create VIs that can be used as reentrant subVIs with configurable I/O items. You can specify the methods and properties available for an FPGA I/O control using the Configure FPGA I/O Name Control Type dialog box. The type you specify in the I/O Name Control Type list of the Configure FPGA I/O Name Control Type dialog box determines the data types of input and output terminals when you wire the FPGA I/O control to the FPGA I/O In input of an FPGA I/O Node, FPGA I/O Method Node, or FPGA I/O Property Node. When you use an FPGA I/O control as an input on a subVI, the input accepts only I/O items that match the specific data type you define for the FPGA I/O control. The I/O item wired to the FPGA I/O control must support a superset of the methods and properties you enable for the FPGA I/O control. All methods must match in name, order, and data type. All properties and I/O must match in name and data type.
For example, the communication device tester shown in the following block diagram uses an FPGA I/O control, DIO Port, configured as an 8-bit digital input and output (DIO) port with the Read, Write, and Set Output Enable methods enabled. In the VI, DIO Port passes an FPGA I/O item to the first FPGA I/O Node. The first FPGA I/O Node writes data to the device under test, driving the port for the time specified by DUT Response Time. Then the I/O Method Node disables output on each line of the port, enabling the device under test to send a response back through DIO Port. The second FPGA I/O Node then reads the response from the device. Finally, the Boolean indicator, Pattern Detected?, indicates whether the response from the device matches the expected response specified by Pattern.
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Note Not all FPGA targets contain DIO port resources. |
You can configure the FPGA I/O control as a connector pane input and use the device tester as a reentrant subVI. On an FPGA target with multiple 8-bit DIO ports, you can use a different I/O port with each instance of the subVI to test multiple devices, as shown in the following block diagram.
The following restrictions apply to FPGA I/O controls:
- You cannot change the value of FPGA I/O controls and indicators while an FPGA VI runs on a development computer or when using Interactive Front Panel communication.
- You cannot access FPGA I/O controls and indicators from the FPGA Interface.
- You can bundle FPGA I/O controls into clusters with other FPGA I/O controls and FPGA clock controls, but not with other data types.
Specifying FPGA Clocks When Calling SubVIs
Use the FPGA clock control, located on the Modern»Name Controls palette, to pass FPGA I/O clocks to the block diagram. For example, the pulse train generator shown in the following block diagram uses an FPGA clock control, Clock, wired to the Source Name input of a Timed Loop.
In the block diagram below, the pulse train generator is configured as a reentrant subVI with an FPGA clock input. FPGA clock constants specify the clocks used in each instance of the subVI.
The following restrictions apply to FPGA clock controls:
- You cannot change the value of FPGA clock controls and indicators while an FPGA VI runs on a development computer or when using Interactive Front Panel communication.
- You cannot access FPGA clock controls and indicators from the FPGA Interface.
- You can bundle FPGA clock controls into clusters with other FPGA clock controls and FPGA I/O controls, but not with other data types.
Using Feedback Nodes in SubVIs
Use a Feedback Node anywhere on the block diagram to store data from a previous VI or loop execution. You can use the Feedback Node and objects with internal registers, such as the Memory Method Node, in subVIs in single-cycle Timed Loops. You also can use the Feedback Node to create reusable subVIs that store state. For example, you can use the Feedback Node with the FPGA I/O control to create a reusable counter.