Using VHDL Code as Component-Level IP (FPGA Module)

LabVIEW 2009 FPGA Module Help

Edition Date: June 2009

Part Number: 371599E-01

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You must be familiar with VHDL and have basic XML knowledge to use component-level intellectual property (CLIP). Use CLIP to instantiate VHDL code with a defined interface that occupies a portion of an FPGA. Unlike the HDL Interface Node, you can use CLIP to perform the following tasks:

Run VHDL code in parallel with LabVIEW code.
Execute VHDL code in multiple clock domains.
Include constraints in the compilation.
Create CLIP clocks

In addition, some FPGA targets support accessing hardware I/O.

Types of CLIP

Support for CLIP varies by FPGA target. Refer to the target hardware documentation for information about CLIP support. Some FPGA targets support one or both of the following types of CLIP:

User-defined CLIP—Enables VHDL code to communicate directly with an FPGA VI.
Socketed CLIP—Enables VHDL code to communicate directly with an FPGA VI and FPGA pins that are not exposed to the LabVIEW FPGA Module. Some FPGA targets define a fixed CLIP socket in the FPGA where you can insert socketed CLIP.

The following illustration shows the relationship between an FPGA VI and CLIP.

Refer to the CLIP Tutorial: Adding Component-Level IP to an FPGA Project for an example of using VHDL code as CLIP.