Requires: FPGA Module
In an FPGA VI, double-click the Input Node of a Timed Loop or right-click the node and select Configure Input Node from the shortcut menu to display this dialog box.
Use this dialog box to configure options on a single-cycle Timed Loop in an FPGA VI.
|Note To specify the clock that controls a single-cycle Timed Loop, you also can use the Source Name input on the Input Node of the Timed Loop. By using an FPGA clock control configured as an input terminal on the connector pane, you can create subVIs with configurable clocks.|
You can specify that a single-cycle Timed Loop uses any clock under the FPGA target in the Project Explorer window. You can have multiple single-cycle Timed Loops on a block diagram, each executing at different clock rates. Double-click the Input Node of a Timed Loop to display this dialog box.
This dialog box includes the following components: