Timing Violation Analysis Window

Requires: FPGA Module

Click the Investigate Timing Violation button in the Compilation Status window to display the Timing Violation Analysis window. The Investigate Timing Violation button appears only if the compile server encounters timing violations while trying to compile an FPGA VI. If the compile server encountered timing violations the last time you compiled a VI, you also can right-click the VI under an FPGA target in the Project Explorer window and select Analyze Timing Violation from the shortcut menu to display this window.

Use this window to identify components in the FPGA application that cannot execute within the application clock rate. Double-click an item in the list or click the Show Element button to locate the node on the block diagram.

This window includes the following components:

• Timing delays (ns)—Lists the propagation delay of components in the FPGA VI that cause the timing violation. The units of Total, Logic, and Routing are in nanoseconds.
  • Paths—Lists sets of VIs and components that exceed the applicable FPGA clock rate. Each path describes the VIs and components between two internal registers. When items in the table correspond to objects on the block diagrams, such as functions, structures, and subVIs, double-clicking the items in the table highlights the corresponding object on the block diagram.
    
    Some items in the table are non-diagram components and do not correspond directly to objects on the block diagrams. Non-diagram components include resources, arbitration circuits, component-level IP (CLIP), and other circuits that depend on the target hardware. You may be able to use the internal name of the non-diagram component to correlate the non-diagram component with a block diagram object or CLIP.
  • Total—Indicates the sum of Logic and Routing. Because of rounding, the value of Total might differ slightly from the sum of the values of Logic and Routing.
  • Logic—Indicates the amount of time in nanoseconds that a logic block takes to execute.
  • Routing—Indicates the amount of time in nanoseconds that a signal takes to traverse between FPGA logic blocks.
• Show Element—Highlights on the block diagram the item you select in the Paths list. You also can double-click an item in the Paths list to highlight the item on the block diagram.
• Show Path—Highlights on the block diagram all items in the path you select in the Paths list.

Fixing Timing Violations

You can use the following strategies to fix a timing violation.

• If the target supports the Xilinx Options page, change some of the compilation options.
• Reduce long combinatorial paths.
• Use pipelining.
• Reduce the number of nested Case Structures.
• Use smaller data types.
• Recompile the FPGA VI. Because the compilation process non-deterministically maps the FPGA VI to the FPGA, the process does not produce the same results each time you compile an FPGA VI. Therefore, if the FPGA VI did not miss the required clock rate by much, recompiling the FPGA VI might fix the timing violation.
• Reduce the clock rate of the application.

Erroneously Listed Single-Cycle Timed Loops

If the FPGA VI uses a large area on the FPGA, the Xilinx compiler optimizations might map different single-cycle Timed Loops to different look-up tables (LUTs) in the same slice. If two different single-cycle Timed Loops map to the same slice and a timing error occurs in one of them, the Timing Violation Analysis window might indicate the wrong single-cycle Timed Loop has the timing violation.