Writing and Reading FIFOs in FPGA VIs (FPGA Module)

Complete the following steps to read from or write to a FIFO in an FPGA VI.

1. Create a new project or open an existing project.
2. Add an FPGA target to the project.
3. Right-click the FPGA target and select New»VI from the shortcut menu to add an FPGA VI to the project. You also can open an existing FPGA VI.
4. Create an FPGA FIFO in the project or using the VI-Defined FIFO Configuration node.
5. Add a FIFO Method Node configured with the Read or Write method to the block diagram of the FPGA VI.
6. Right-click the FIFO Method Node and select Select FIFO»x from the shortcut menu, where x is the name of the FPGA FIFO item in the Project Explorer window or the VI-defined FIFO item on the block diagram. LabVIEW prepends VI:: to the name of VI-defined FIFO items.

You also can drag the FPGA FIFO item in the Project Explorer window to the FPGA VI block diagram. When you drag a FIFO to the block diagram, LabVIEW adds a FIFO Method Node configured with the FIFO and the Write method to the block diagram.

Note  If you use the FIFO Method Node configured with the Read or Write methods in a single-cycle Timed Loop, you must wire a constant of zero to the Timeout parameter.

Refer to Reading DMA FIFOs from Host VIs and Writing to DMA FIFOs from Host VIs for more information about using DMA FIFOs in host VIs.