Using FPGA Clocks and Timing (FPGA Module)

A base clock is a digital signal existing in hardware that you can use as a clock for an FPGA application. A derived clock is a clock you create from a base clock that you can use as a clock for an FPGA application. The top-level clock is the global clock that the FPGA VI uses outside a single-cycle Timed Loop. LabVIEW uses the base clock properties when setting timing constraints on circuits generated from the FPGA VI during compilation.

Every VI or function you place in an FPGA VI takes a certain amount of time, known as logic delay, to execute. The top-level clock on an FPGA target determines the execution time of the individual functions and VIs on the FPGA VI block diagram. If you change the frequency of the top-level clock, you also change the operation speed of functions on the block diagram and the execution rate of the FPGA VI.

By controlling the execution rate of the FPGA application, you specify the timing objectives of an FPGA application. You can allow operations to occur at the rate determined by the dataflow without additional programming. If you want to control or measure the execution timing, use the Timing VIs. You also can use the Timing VIs to create custom I/O applications such as counters and triggers.