LabVIEW 2009 FPGA Module Help
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You can define a top-level clock for an FPGA target in the Project Explorer window. The top-level clock is the global clock that the FPGA VI uses outside a single-cycle Timed Loop. The FPGA target uses one of the FPGA base clocks by default. Complete the following steps to select a top-level timing source for an FPGA target.
- Create a new project or open an existing project.
- Add an FPGA target to the project.
- If the FPGA target you use does not automatically add an FPGA base clock to the Project Explorer window, add the FPGA base clock. If you want to use the FPGA base clock as the timing source for the top-level clock, skip the following step.
- (Optional) Create an FPGA derived clock.
- Right-click the FPGA target in the Project Explorer window and select Properties from the shortcut menu. The FPGA Target Properties dialog box appears.
- Select Top-Level Clock in the Category list.
- Select Default if you want to use the default FPGA target clock. Select Select Configured Clock and a configured clock from the Configured Clock list if you want to use a clock you configured.
- Click the OK button.
Note Some FPGA targets do not allow certain configured clocks as top-level clocks. |