You can create Direct Memory Access (DMA) FIFOs in FPGA VIs to transfer data from FPGA VIs to host VIs. Some FPGA targets do not support DMA. The FPGA targets that support DMA include a fixed number of DMA channels available for transferring data between the FPGA VI and the host VI. Refer to the specific FPGA target or chassis hardware documentation for information about the number of DMA channels available, if the FPGA target supports DMA.
Complete the following steps to read a DMA FIFO in an FPGA VI.
|Note The FPGA target, FPGA VI, and host VI must be in the same LabVIEW project if you want to open a reference to an FPGA VI. The host VI does not need to be in a project if you open a reference to a bitfile. If you open a reference to an FPGA VI, the project must include a DMA FIFO item under the FPGA target and the FPGA VI must include a FIFO Method Node configured with the Write method on the block diagram that writes to the DMA FIFO item.|
|Note You can read DMA FIFOs using only the Invoke Method function with the Read method. If you want more control over the DMA FIFO from the host VI, you also can configure, start, and stop the DMA FIFO using the optional Configure, Start, and Stop methods with the Invoke Method function.|