Version 2009 Features and Changes (FPGA Module)
Refer to the LabVIEW Features and Changes topic for information about new features in LabVIEW. Refer to the LabVIEW FPGA Release and Upgrade Notes for information about upgrade and compatibility issues specific to different versions of the FPGA Module. Refer to ni.com for information about known issues with the FPGA Module.
The FPGA Module 2009 includes the following new features to help you better manage and implement the components of an FPGA application.
Timing Violation Analysis Window
You can use the new Timing Violation Analysis window to identify components in the FPGA VI that cannot execute within a specified clock rate.
If the Compilation Status window reports timing violation errors, you can click the Timing Violation Analysis button to display the Timing Violation Analysis window. The window lists the propagation delay of the FPGA VI components that cause the timing violation. You can double-click an item in the list to locate the node on the block diagram.
Compilation Process Improvements
Configuring Xilinx Compilation Options
If the target supports the new Xilinx Options page in the FPGA Target Properties dialog box, you can adjust options Xilinx uses to compile the FPGA VI. In general, you do not need to adjust the options on this page unless the FPGA VI fails to compile. Use the information from the Compilation Status window to determine which options on this page might help the FPGA VI compile successfully.
Improved Feedback when Compiling FPGA VIs
With the new Compilation Status window, LabVIEW now provides information throughout the compilation process that can help you monitor the compilation status and more quickly determine whether the FPGA VI will meet the resource and timing constraints of the FPGA.
The progress bar in the Compilation Status window indicates the current step in the Xilinx compilation process. You can watch the progress bar as you continue working in LabVIEW. In addition, you can disconnect from the compilation server through the Compilation Status window and queue up multiple VIs to compile.
Math and Analysis VIs and Functions Improvements
High Throughput Math Functions
Use the High Throughput Math functions to perform high-throughput math and analysis with fixed-point numbers on FPGA targets. These functions are similar to the Numeric functions but support higher throughput rates, handshaking terminals inside a single-cycle Timed Loop, internal input/output registers, and automatic pipelining. You also can use these functions outside a single-cycle Timed Loop.
The following is a list of new functions:
- High Throughput Add
- High Throughput Divide
- High Throughput Exponential
- High Throughput Hyperbolic Sine & Cosine
- High Throughput Inverse Tangent
- High Throughput Multiply
- High Throughput Natural Logarithm
- High Throughput Polar to Rectangular
- High Throughput Reciprocal
- High Throughput Rectangular to Polar
- High Throughput Sine & Cosine
- High Throughput Square Root
- High Throughput Subtract
- High Throughput To Fixed-Point
Scaling VIs
Use the Scaling VIs in host VIs to convert the clock and sample rate for the Loop Timer Express VI and to reconfigure input settings and post-process data from the FPGA Math & Analysis VIs. The Scaling VIs are located on the FPGA Interface palette for host VIs under an RT or My Computer target. The following is a list of new VIs:
- Butterworth Coefficients
- FFT to Spectrum
- Normalize Signal Generation Parameters
- Notch Coefficients
- Sample Rate to Loop Time
- Scale Period
FIFO and Memory Improvements
FIFO and Memory Name Controls
You can use the FIFO and Memory name controls to pass FIFO and memory references to and from VIs, just like you use the FPGA I/O name control and the FPGA Clock name control. You also can use FIFO and Memory constants to reference FIFO and memory items.
New FIFO Methods
The FPGA FIFOs support the following FIFO methods.
Implement Memory Using LUTs
You can use look-up tables (LUTs) as well as embedded block memory to implement memory items in an FPGA VI. Using LUTs for memory items, especially memory items with a small number of elements, reserves embedded block memory for other functions.
Support for the Enhanced Feedback Node
FPGA VIs support the multi-cycle delays, enable signals, and initialization options of the enhanced Feedback Node. If you place this node in an FPGA VI, you can specify that the Xilinx compiler implement this node by using shift register look-up tables (SRLs) instead of flip-flops. This change improves resource usage on FPGA targets.
Support for User-Defined I/O Variables
If you execute an FPGA VI on an FPGA target that supports the NI Scan Engine, you can create user-defined I/O variables to send I/O data between that the FPGA VI and an RT VI running on a single controller.
Refer to the Fundamentals»Accessing Scanned I/O Data»Concepts book on the Contents tab for general information about the NI Scan Engine and I/O variables.
CLIP Improvements
Specifying Clock Domains for CLIP I/O
Use the following XML tags in a CLIP declaration file to avoid metastable data in CLIP I/O.
- RequiredClockDomain—If you require a clock domain, any I/O Node on the block diagram that uses this CLIP I/O must be within the clock domain you specify.
- UseInLabVIEWSingleCycleTimedLoop—If you require that the IP in the CLIP get or receive values on every clock edge, setting this tag makes LabVIEW enforce this requirement.
Clocks Defined in CLIP
You can instantiate clock circuitry in a CLIP and use CLIP clocks in the same way you use other clocks that the target provides. You also can route external clocks supplied by socketed CLIPs to LabVIEW. Clocks in the CLIP declaration file appear automatically under the CLIP item in the Project Explorer window.
LabVIEW treats CLIP clocks like external clocks, except that you cannot use the Start Enabling FPGA Clock and Start Disabling FPGA Clock VIs with CLIP clocks to protect circuitry when the clock might not be available.
Additional Data Types for CLIP
CLIP supports the I64 and U64 data types.