Array Palette Details (FPGA Module)

LabVIEW 2011 FPGA Module Help

Edition Date: June 2011

Part Number: 371599G-01

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This topic contains FPGA-specific information about the objects on the Array Functions palette.

Note The information in this topic is subject to change with each version of the LabVIEW FPGA Module.

Array Constant

Single-Cycle Timed Loop	Supported.
Usage	N/A
Timing	This function requires no clock cycles to execute because it does not include an internal register.
Resources	This function alone consumes no logic resources on the FPGA. However, when the array constant is wired to a logic operation, the array uses FPGA lookup table resources. Large arrays can be time and resource intensive if you perform logical operations on each element of the array.

Array Size

Single-Cycle Timed Loop	Supported.
Usage	N/A
Timing	This function requires no clock cycles to execute because it does not include an internal register.
Resources	This function consumes no logic resources on the FPGA because it is purely a wiring operation.

Array Subset

Single-Cycle Timed Loop	Supported.
Usage	The LabVIEW FPGA Module supports only 1D fixed-size arrays. You must wire a constant to the index and length inputs so that LabVIEW can determine the size of subarray.
Timing	This function requires no clock cycles to execute because it does not include an internal register.
Resources	This function consumes no logic resources on the FPGA because it is purely a wiring operation.

Array To Cluster

Single-Cycle Timed Loop	Supported.
Usage	N/A
Timing	This function requires no clock cycles to execute because it does not include an internal register.
Resources	This function consumes no logic resources on the FPGA because it is purely a wiring operation.

Build Array

Single-Cycle Timed Loop	Supported.
Usage	The LabVIEW FPGA Module supports only 1-D fixed-size arrays. To make sure this function can output a fixed-size array, open the VI Properties dialog box, select Execution from the Category pull-down menu, and place a check in the Autopreallocate arrays and strings checkbox.
Timing	This function requires no clock cycles to execute because it does not include an internal register.
Resources	This function consumes no logic resources on the FPGA because it is purely a wiring operation.

Cluster To Array

Single-Cycle Timed Loop	Supported.
Usage	The LabVIEW FPGA Module supports only 1-D fixed-size arrays. To make sure this function can output a fixed-size array, open the VI Properties dialog box, select Execution from the Category pull-down menu, and place a check in the Autopreallocate arrays and strings checkbox.
Timing	This function requires no clock cycles to execute because it does not include an internal register.
Resources	This function consumes no logic resources on the FPGA because it is purely a wiring operation.

Decimate 1D Array

Single-Cycle Timed Loop	Supported.
Usage	N/A
Timing	This function requires no clock cycles to execute because it does not include an internal register.
Resources	This function consumes no logic resources on the FPGA because it is purely a wiring operation.

Delete From Array

Single-Cycle Timed Loop	Supported.
Usage	The LabVIEW FPGA Module supports only 1D fixed-size arrays. You must wire a constant to the index and length inputs so that LabVIEW can determine the size of array w/ subset deleted and deleted portion.
Timing	This function requires no clock cycles to execute because it does not include an internal register.
Resources	This function consumes no logic resources on the FPGA because it is purely a wiring operation.

Index Array

Single-Cycle Timed Loop	Supported.
Usage	N/A
Timing	This function executes in one clock cycle, unless you wire a constant immediately into the index input, in which case the selection occurs at compile time and the function requires no clock cycles.
Resources	This function consumes logic resources in proportion to the size of the array.

Note For large arrays, the Index Array function might not be able to execute within a single clock cycle, resulting in a compile-time error.

Initialize Array

Single-Cycle Timed Loop

Supported.

Usage

The LabVIEW FPGA Module supports only 1D fixed-size arrays, so you must wire a constant directly to the dimension size input so that LabVIEW knows the size of the output array. To make sure this function can output a fixed-size array, open the VI Properties dialog box, select Execution from the Category pull-down menu, and place a check in the Autopreallocate arrays and strings checkbox.

Note Although the size of the array you initialize does not affect the timing and resource usage of this function, large arrays can be time and resource intensive when you perform logical operations on the elements of the array.

Timing

This function requires no clock cycles to execute because it does not include an internal register.

Resources

This function consumes no logic resources on the FPGA because it is purely a wiring operation.

Insert Into Array

Single-Cycle Timed Loop	Supported.
Usage	If the index input is beyond the range of the array into which you are inserting elements, this function does not insert anything into the input array. The LabVIEW FPGA Module supports only 1D fixed-size arrays, so you must wire a constant directly to the index input so that LabVIEW knows the size of the output array at compile time.
Timing	This function requires no clock cycles to execute because it does not include an internal register.
Resources	This function consumes no logic resources on the FPGA because it is purely a wiring operation.

Interleave 1D Arrays

Single-Cycle Timed Loop	Supported.
Usage	N/A
Timing	This function requires no clock cycles to execute because it does not include an internal register.
Resources	This function consumes no logic resources on the FPGA because it is purely a wiring operation.

Replace Array Subset

Single-Cycle Timed Loop

Supported.

Usage

N/A

Timing

This function executes in one clock cycle. However, if you wire a constant immediately into the index input, the selection occurs at compile time and the function requires no clock cycles.

Note For large arrays, the Replace Array Subset function might not be able to execute within a single clock cycle, resulting in a compile-time error.

Resources

This operation consumes logic resources in proportion to the size of the array.

Reshape Array

Single-Cycle Timed Loop	Supported.
Usage	The LabVIEW FPGA Module supports only 1D fixed-size arrays, so you must wire a constant directly to the dimension size input so that LabVIEW knows the size of the output array.
Timing	This function requires no clock cycles to execute because it does not include an internal register.
Resources	This function consumes no logic resources on the FPGA because it is purely a wiring operation.

Reverse 1D Array

Single-Cycle Timed Loop	Supported.
Usage	N/A
Timing	This function requires no clock cycles to execute because it does not include an internal register.
Resources	This function consumes no logic resources on the FPGA because it is purely a wiring operation.

Rotate 1D Array

Single-Cycle Timed Loop	Not Supported.
Usage	If you wire a constant directly to the n input, this function is purely a wiring operation. Otherwise, this function implements an iterative algorithm, rotating the elements by one position each clock cycle.
Timing	If n is a constant, this operation requires no clock cycles. Otherwise, this operation takes n clock cycles to execute, plus three clock cycles of overhead.
Resources	If you wire a constant directly to the n input, this operation consumes no logic resources. Otherwise, this operation consumes logic resources in proportion to the size of the array.

Split 1D Array

Single-Cycle Timed Loop	Supported.
Usage	The LabVIEW FPGA Module supports only 1D fixed-size arrays, so you must wire a constant directly to the index input so that LabVIEW knows the size of the output array.
Timing	This function requires no clock cycles to execute because it does not include an internal register.
Resources	This function consumes no logic resources on the FPGA because it is purely a wiring operation.