Comparison Palette Details (FPGA Module)
This topic contains FPGA-specific information about the objects on the Comparison Functions palette.
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Note The information in this topic is subject to change with each version of the LabVIEW FPGA Module. |
The following details apply to all the Comparison functions, except for the Max & Min function.
| Single-Cycle Timed Loop | Supported. |
| Usage | When you compare signed and unsigned integers of the same width, such as U8 and I8, LabVIEW treats both integers as unsigned integers. |
| Timing | Inside single-cycle Timed Loop—When you use Comparison functions inside a single-cycle Timed Loop, the combinatorial logic delay is proportional to the width of the data types you compare.
Outside single-cycle Timed Loop—When you use Comparison functions outside a single-cycle Timed Loop, each Comparison function takes one clock cycle. If you use the Comparison functions with the fixed-point data type, the overflow and rounding modes might impact timing. |
| Resources | The Comparison functions use FPGA logic resources in proportion to the width of the data types you compare. |
Max & Min
| Single-Cycle Timed Loop | Supported. |
| Usage | You cannot wire an array or cluster to this function in an FPGA VI. When you compare signed and unsigned integers of the same width, such as U8 and I8, LabVIEW treats both integers as unsigned integers. |
| Timing | Inside single-cycle Timed Loop—When you use Comparison functions inside a single-cycle Timed Loop, the combinatorial logic delay is proportional to the width of the data types you compare.
Outside single-cycle Timed Loop—When you use Comparison functions outside a single-cycle Timed Loop, each Comparison function takes one clock cycle. |
| Resources | The Comparison functions use FPGA logic resources in proportion to the width of the data types you compare. |