Conversion Palette Details (FPGA Module)

LabVIEW 2011 FPGA Module Help

Edition Date: June 2011

Part Number: 371599G-01

»View Product Info

This topic contains FPGA-specific information about the objects on the Conversion Functions palette.

Note The information in this topic is subject to change with each version of the LabVIEW FPGA Module.

The following details apply to all the Conversion functions, except the Boolean Array to Number, Number to Boolean Array, and To Fixed-Point functions.

Single-Cycle Timed Loop	Supported.
Usage	N/A
Timing	The Conversion functions require no clock cycles to execute because they do not include internal registers. If you use the Conversion functions with the fixed-point data type, the overflow and rounding modes might impact timing.
Resources	The Conversion functions consume no logic resources on the FPGA because they are purely wiring operations. If you use the Conversion functions with the fixed-point data type, the overflow and rounding modes might impact resources.

Boolean Array to Number

The following details apply to the Boolean Array to Number function.

Single-Cycle Timed Loop	Supported.
Usage	The FPGA Module supports only 1-D fixed-size arrays. The Boolean Array To Number function converts fixed-size arrays to use the smallest unsigned representation that will fit the array size.
Timing	This function requires no clock cycles to execute because it does not include internal registers.
Properties Dialog Box	The data type of number changes based on the size of the array when the Adapt to source checkbox in the Output Configuration page contains a checkmark. For example, if Boolean array is a bounded array of 9, number has a data type of U16.
Resources	This function consumes no logic resources on the FPGA because it is purely a wiring operation.

Number to Boolean Array

The following details apply to the Number to Boolean Array function.

Single-Cycle Timed Loop	Supported.
Usage	The LabVIEW FPGA Module supports only 1-D fixed-size arrays. To make sure this function can output a fixed-size array, open the VI Properties dialog box, select Execution from the Category pull-down menu, and place a check in the Autopreallocate arrays and strings checkbox.
Timing	This function requires no clock cycles to execute because it does not include an internal register.
Resources	This function consumes no logic resources on the FPGA because it is purely a wiring operation.

To Fixed-Point

The following details apply to the To Fixed-Point function.

Single-Cycle Timed Loop	Supported.
Usage	N/A
Timing	This function requires no clock cycles if you select the Wrap overflow mode and Truncate rounding mode. Other overflow and rounding modes might impact timing.
Resources	This function consumes no logic resources on the FPGA if you select the Wrap overflow mode and Truncate rounding mode. Other overflow and rounding modes might impact resources.

Note You also can use the High Throughput To Fixed-Point function to perform fixed-point math and analysis on an FPGA target.