LabVIEW 2011 FPGA Module Help
Edition Date: June 2011
Part Number: 371599G-01
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Because FPGAs operate differently than standard PC processors, you need to keep in mind different considerations when you create a VI to run on an FPGA target versus when you create a VI to run on a PC. The following palettes contain objects with FPGA-specific considerations.
The details for each palette object include a table with the following FPGA-specific considerations.
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Single-Cycle Timed Loop—Specifies whether you can use the VI or function inside a single-cycle Timed Loop.
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Usage—Contains information about the behavior of the VI or function when used in an FPGA VI.
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Timing—Contains information about the amount of time the VI or function takes to execute. Outside the single-cycle Timed Loop, this information refers to the number of clock cycles a VI or function takes to execute. Inside the single-cycle Timed Loop, this information refers to the combinatorial path length of the VI or function.
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Resources—Contains information about the FPGA logic resource usage of the VI or function.