Owning Palette: Timed Structures
Requires: FPGA Module
The FPGA Module Timed Loop differs from the standard LabVIEW Timed Loop in that the timing of the FPGA Timed Loop corresponds exactly to the clock rate of the FPGA clock you specify. By configuring a single-cycle Timed Loop to use a clock other than the base clock of the FPGA target, you can implement multiple clock domains in an FPGA VI. You can specify the FPGA clock that controls the Timed Loop by wiring a value to the Source Name input on the Input Node of the Timed Loop or by using the Configure Timed Loop dialog box.
You can use most VIs and functions available when you target an FPGA target in a single-cycle Timed Loop. However, you cannot use the following VIs, functions, and structures in a single-cycle Timed Loop. LabVIEW reports a code generation or compile-time error for the single-cycle Timed Loop when you try to compile an FPGA VI with any of the following VIs, functions, or structures in a single-cycle Timed Loop.
The FPGA target you use might not support additional VIs or functions. Also, some targets do not support specific I/O items both inside and outside a single-cycle Timed Loop. Refer to the specific FPGA target hardware documentation for more information.
The following tables described how Timed Loops interact with other components.
|Timed Loops Open in VIs under My Computer||If you place the Timed Loop in a VI open under My Computer, the Timed Loop displays some terminals that FPGA targets do not support. So, if you open the VI under an FPGA target, the unsupported terminals still appear. If you place the Timed Loop in a VI open under an FPGA target, the Timed Loop hides terminals that are not supported. So, if you open the VI under My Computer, the Timed Loop does not display all terminals that My Computer supports.|
|Timed Loops Open in VIs under an FPGA Target||When you place a Timed Loop in an FPGA VI, only the Source Name input appears visible by default. Other than Source Name and Error, the inputs available on the Input Node of the Timed Loop have no effect when you use the Timed Loop in an FPGA VI. Error is the only supported output of the Timed Loop in an FPGA VI. |
|Indicators in Single-Cycle Timed Loops||You can place indicators in the single-cycle Timed Loop only if you do not have any local variables writing to the indicators.|
|FPGA I/O Nodes and Timed Loops||You can use the FPGA I/O Node in the single-cycle Timed Loop if the FPGA target allows it. If the FPGA target you use supports the single-cycle Timed Loop, you can use only the Arbitrate if Multiple Requestors Only and Never Arbitrate arbitration options. If you select Arbitrate if Multiple Requestors Only, you cannot use more than one instance of the FPGA I/O Node for a specific I/O item in the FPGA VI. If you select Never Arbitrate, you can use more than one instance of the FPGA I/O Node for a specific I/O item in the FPGA VI if each instance is in a single-cycle Timed Loop executing at the same rate.|
|Flat Sequences and Timed Loops||You can use the Flat Sequence or Stacked Sequence structure in the single-cycle Timed Loop. However, all sequence frames execute in one clock cycle.|
|SubVIs and Timed Loops||You cannot use more than one instance of a non-reentrant or shared subVI in a single-cycle Timed Loop. You can use multiple instances of a reentrant VI inside a single-cycle Timed Loop as long as the reentrant VI does not use shared resources.|
|Wait On Occurrence Function and Timed Loops||You cannot use the Wait on Occurrence function in a single-cycle Timed Loop. However, you can use the Set Occurrence function. You then can use the Wait on Occurrence function outside the single-cycle Timed Loop in a While Loop or For Loop.|
You can use some functions in the single-cycle Timed Loop that take one clock cycle to execute, such as the Memory Method Node. If you use this function to read from a memory item that uses embedded block memory, the output of this function is not valid until the next iteration of the single-cycle Timed Loop. Therefore, you must wire the outputs of such functions directly to uninitialized shift registers.
|Note Functions such as the Memory Method Node, FFT Express VI, and FPGA I/O, have internal registers that can appear as paths in the Timing Violation Analysis window.|