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Transferring Data between Devices or Structures Using FIFOs (FPGA Module)

LabVIEW 2011 FPGA Module Help

Edition Date: June 2011

Part Number: 371599G-01

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To transfer data between different portions of an FPGA VI, between VIs in an FPGA target, or between devices, use a FIFO. A FIFO is a data structure that holds elements in the order they are received and provides access to those elements using a first-in, first-out access policy. When you configure a FIFO, you must specify the implementation that determines which FPGA resources hold and transfer data in the FIFO.

The following illustration demonstrates the behavior of elements moving through a FIFO.

Use FIFOs to transfer data in the following ways:

Use the FIFO Properties dialog box to create and configure FIFOs.

All FIFOs except VI-defined FIFOs have a corresponding item in the project. Therefore, if you use a FIFO other than a VI-defined FIFO and send the FPGA VI to another user, you must send the entire project. Otherwise, the FPGA VI is broken.

Use the following flow chart to determine the FIFO configuration that best fits your application needs.

The following figure shows an example of a target-scoped FIFO used to transfer data between two single-cycle Timed Loops in the same FPGA VI. The single-cycle Timed Loops are in two different clock domains. The top loop uses an 80 MHz clock and the bottom loop uses a 40 MHz clock. In this example, an FPGA I/O Node in the 80 MHz clock domain acquires temperature readings from a device. A FIFO Method node writes the data to a FIFO. If the data is not available to write immediately, the node times out, stops the loop, and sets the Write Timed Out? indicator to TRUE. A FIFO Method node in the 40 MHz clock domain reads the data, then passes the data to a Less Than 0? function. If the temperature is less than zero, the function sets the Device Frozen? indicator to TRUE. If the data is not available to read immediately, the FIFO Method node times out, stops the loop, and sets the Read Timed Out? indicator to TRUE.

Note  The following figure shows an example of the programming concepts discussed in this topic. However, different programming needs might require that you implement these programming concepts differently.

Note  If the FIFO Method Node contains a Timeout input parameter, you must wire the parameter to a constant of zero when the node is in a single-cycle Timed Loop.

Data Transfer Tasks

You can transfer data in the following ways:

  • Within one FPGA target—Use these types of FIFOs to transfer data between VIs, to and from loops in a single VI, or between clock domains.
    • Target-scoped FIFOs—Use target-scoped FIFOs if you want the FIFO to be visible and configurable from the Project Explorer window. Target-scoped FIFOs have a corresponding item in the project. Updates to the project item affect all instances of the FIFO. Target-scoped FIFOs are accessible within any VI under the same FPGA target in the Project Explorer window. If you use a target-scoped FIFO and want to send the FPGA VI to another user, you have to send the entire project. Otherwise, the FPGA VI is broken.
    • VI-defined FIFOs— Use VI–defined FIFOs along with FIFO name controls to create reentrant subVIs and avoid resource conflicts. If you configure a VI-defined FIFO in a reentrant FPGA VI, LabVIEW creates a separate copy of the FIFO for each instance of the VI.
  • Between the host and the FPGA—Use direct memory access (DMA) FIFOs to transfer large amounts of data between the host and the FPGA. This type of FIFO directly accesses memory to transfer data from FPGA target VIs to host VIs and vice versa. A DMA FIFO allocates memory on both the host computer and the FPGA target, yet acts as a single FIFO. DMA FIFOs provide performance advantages over using front panel controls and indicators to communicate between the host and the FPGA.
  • Between two peer-to-peer targets—Use peer-to-peer FIFOs to transfer data between peer-to-peer targets without sending the data through the host. You can use peer-to-peer streaming to send data between FPGA and non-FPGA targets, but the targets must be capable of using the peer-to-peer stream architecture. Peer-to-peer FIFOs have a corresponding item in the project.
Note  If you include multiple reads or writes to the same FIFO, the FIFO can become a shared resource. To prevent data corruption and jitter, avoid simultaneous read or write requests to a single FIFO.

Steps to Create FIFOs in LabVIEW

Creating a Target-Scoped FIFO from the Project Explorer Window

Complete the following steps to create a target-scoped FIFO from the Project Explorer window.

  1. In the Project Explorer window, right-click the FPGA target.
  2. Select New»FIFO to display the FIFO Properties dialog box.
  3. In the FIFO Properties dialog box, expand the pull-down menu under Implementation to display the available options.
  4. Click the OK button to finish creating the FIFO.
  5. Drag the FIFO from the Project Explorer window to the block diagram. LabVIEW adds a FIFO Method node configured for the FIFO.

Creating a FIFO from the Block Diagram

You can create either a target-scoped or a VI-defined FIFO from the block diagram.

Complete the following steps to create a target-scoped FIFO.

  1. Display the block diagram.
  2. From the Functions palette, select Memory & FIFO»FIFO Method Node and add it to the block diagram.
  3. Right-click the FIFO Method node and select Add New FIFO from the shortcut menu to create a new FIFO and display the FIFO Properties dialog box.
  4. In the FIFO Properties dialog box, expand the Implementation pull-down menu to display the available options.
  5. Click the OK button to finish creating the FIFO.

Complete the following steps to create a VI-defined FIFO.

  1. Display the block diagram.
  2. From the Functions palette, select Memory & FIFO»VI-Defined FIFO Configuration Node and add it to the block diagram.
  3. Right click the VI-Defined FIFO Configuration node and select Configure from the shortcut menu to display the FIFO Properties dialog box.
  4. In the FIFO Properties dialog box, expand the Implementation pull-down menu to display the available options. See below for help determining the appropriate implementation.
  5. Click the OK button to finish creating the FIFO.

When you configure a node on the block diagram to use a VI-defined FIFO, LabVIEW prepends VI:: to the name of that FIFO. For example, if you name your VI-defined FIFO Coefficients, LabVIEW displays the name of that FIFO as VI::Coefficients.

Creating a DMA FIFO from the Project Explorer Window

Complete the following steps to determine whether your target supports DMA FIFOs.

  1. In the Project Explorer window, right-click the FPGA target.
  2. Select Properties from the shortcut menu to display the FPGA Target Properties dialog box.
  3. Refer to the Target Information box on the General page to find DMA support information. If your target supports DMA, the Target Information box gives the number of DMA channels. If your target does not support DMA, the Target Information box indicates that DMA is not supported.

Complete the following steps to create a DMA FIFO in an FPGA VI. Refer to Reading DMA FIFOs from Host VIs and Writing DMA FIFOs from Host VIs for help configuring a host VI to read and write DMA FIFOs.

  1. In the Project Explorer window, right-click the FPGA target.
  2. Select New»FIFO to display the FIFO Properties dialog box.
  3. Use the Type pull-down menu to select either Host to Target—DMA or Target to Host—DMA, depending on which direction you want to stream the data.
  4. Click the OK button to finish creating the FIFO.
  5. Drag the FIFO from the Project Explorer window to the block diagram. LabVIEW adds a FIFO Method node configured for the FIFO.

Creating a Peer-to-Peer FIFO from the Project Explorer Window

Complete the following steps to create a peer-to-peer FIFO from the Project Explorer window or to determine whether a particular target supports peer-to-peer streaming.

  1. In the Project Explorer window, right-click the FPGA target.
  2. Select New»FIFO to display the FIFO Properties dialog box.
  3. In the FIFO Properties dialog box, select Peer to Peer Writer or Peer to Peer Reader from the Type pull-down menu. If these options are not available in the pull-down menu, the target does not support peer-to-peer FIFOs.
  4. Click the OK button to finish creating the FIFO.

Refer to the topics on using peer-to-peer streaming with FPGA targets for information about how to use peer-to-peer FIFOs.

Understanding the Implementation Options

If you understand the available FIFO implementation options, then you can create more efficient FPGA designs. Use the FIFO Properties dialog box to specify how a target-scoped or VI-defined FIFO is implemented. DMA and peer-to-peer FIFOs always use block memory. Expand the Implementation pull-down menu to display the available FPGA resource options for the FIFO, as shown in the following illustration.

Note  Refer to the FIFO Properties dialog box topic for help configuring the remaining options in this dialog box.
  • Flip-Flops—Flip-flops are FPGA resources that you can use for data storage or other tasks, such as addition and subtraction. For this reason, flip-flops are often the least abundant FPGA resource for moving or storing data.
    Note  You cannot use FIFOs implemented using flip-flops across multiple clock domains.
  • Look-up Tables (LUTs)—Look-up tables, also known as distributed RAM, consist of logic gates hard-wired on the FPGA. Like flip-flops, LUTs can function as logic resources.
    Note  You cannot use FIFOs implemented using look-up tables across multiple clock domains.
  • Block Memory—Block memory, also known as block random access memory, block RAM or BRAM, is a dedicated FPGA resource for data storage. Refer to Restrictions on Implementing Block Memory FIFOs for more information about using control logic with a block memory implementation. If you configure a target-scoped or VI-defined FIFO using block memory, you can configure the control logic. DMA and peer-to-peer FIFOs can use only block memory.
    Note  If you select the Block Memory option, you might not be able to read data in a target-scoped or VI-defined FIFO until up to six clock cycles after you write the data to the FIFO. Use the Timed Out? output of the FIFO Method Node configured with the Read or Write method to determine whether the data is ready.

 

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