The fixed-point data type provides some of the flexibility of the floating-point data type, which you cannot use on FPGA targets, but maintains the size and speed advantages of integer arithmetic. The following two KnowledgeBase articles provide more information about the fixed-point data type:
|Note Not all FPGA Module VIs and functions support the fixed-point data type. Furthermore, some functions offer only limited fixed-point support. For example, the Sine Wave Generator Express VI supports fixed-point numbers for only the input terminals.|
|Caution If you wire a fixed-point number to an integer, you might lose fractional bits.|
When using fixed-point numbers in an FPGA VI, it is important to select the proper overflow and rounding modes for a particular function. The High Throughput Math functions and some Numeric functions have configuration dialog boxes you use to select these modes. If overflow or rounding can occur, these modes affect the amount of FPGA resources an FPGA VI needs. If overflow or rounding cannot occur, the operation does not require additional FPGA resources.
In many situations, you can avoid overflow by placing a checkmark in the Adapt to source checkbox in the configuration dialog box of the function. If you place a checkmark in this checkbox, LabVIEW attempts to adjust the width and range of the output data type such that neither overflow nor rounding occurs. However, this adjustment is not possible in all situations. For example, if a function involves division, rounding always occurs. Also, some functions do not have this checkbox.
In general, the overflow modes affect FPGA resource usage in the following ways:
In general, the rounding modes affect FPGA resource usage in the following ways:
|Note The High Throughput Divide and High Throughput Reciprocal functions use a rounding mode that truncates the output value towards zero. This mode rounds the output value down to the nearest value that the output type can represent. If the value is positive, LabVIEW truncates the value. If the value is negative, LabVIEW deletes the least significant bits (LSBs) and adds the sign bit to the remaining LSBs, provided at least one of the deleted bits differs from 0.
For example, if the output value x falls between successive values s and t such that s < x < t, LabVIEW sets x to equal s if x is positive. If x is negative, LabVIEW sets x to equal t.
For these two functions, truncating towards zero uses the least amount of FPGA resources compared with the other rounding modes. You cannot specify a different rounding mode for these functions.