Compiling an FPGA VI can take minutes to hours. However, you can test the logic of an FPGA VI before compiling it by running the FPGA VI on a development computer with simulated I/O. When you run an FPGA VI on a development computer with simulated I/O, LabVIEW generates random data for the inputs or uses a custom VI test bench that you create to provide I/O. On some FPGA targets, you also can run the FPGA VI on a development computer with real I/O.
When you run the FPGA VI on the development computer, you can use all traditional LabVIEW debugging techniques, such as probes, execution highlighting, breakpoints, and single-stepping. However, you cannot test certain behavior, such as timing and determinism.
(Statechart) You also can debug statecharts for an FPGA target on the development computer.