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Linear Algebra Dot Product Function

LabVIEW 2013 FPGA Module Help

Edition Date: June 2013

Part Number: 371599J-01

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Owning Palette: Linear Algebra Functions

Requires: FPGA Module

Computes the dot product of two complex vectors.

This function supports only scalar and 1D fixed-size array values of the fixed-point data type.

Details  

Dialog Box Options
Block Diagram Inputs
Block Diagram Outputs

Dialog Box Options

ParameterDescription
Input Vector ConfigurationSpecifies the encodings, word lengths, and integer word lengths of the input terminals of this function.
  • xr/xi Type—Specifies the configuration of the real or imaginary xr/xi input terminals.

    If you wire a fixed-point data type to these terminals, LabVIEW dims this section and uses information from the wire. The xr/xi inputs of this function must be of the same data type and input pattern, otherwise the data type or array size of the xr input terminal takes precedent.
    • Signed—Specifies that these terminals are signed.
    • Unsigned—Specifies that these terminals are unsigned.
    • Word length—Specifies the word length of these terminals.
    • Integer word length—Specifies the integer word length of these terminals.
  • yr/yi Type—Specifies the configuration of the real or imaginary yr/yi input terminals.

    If you wire a fixed-point data type to these terminals, LabVIEW dims this section and uses information from the wire. The yr/yi inputs of this function must be of the same data type and input pattern, otherwise the data type or array size of the yr input terminal takes precedent.
    • Signed—Specifies that these terminals are signed.
    • Unsigned—Specifies that these terminals are unsigned.
    • Word length—Specifies the word length of these terminals.
    • Integer word length—Specifies the integer word length of these terminals.
  • Vector size—Specifies the size of the input vector.
OperationSpecifies whether to conjugate the inputs during operation and specifies the encodings, word lengths, and integer word lengths of the output terminals of this function.
  • Conjugate X—Specifies whether to conjugate the inputs of vector X during operation. Selecting this option does not require additional FPGA resources. LabVIEW displays an icon on the block diagram based on the conjugation option you choose. By default, this checkbox does not contain a checkmark.
  • Conjugate Y—Specifies whether to conjugate the inputs of vector Y during operation Selecting this option does not require additional FPGA resources. LabVIEW displays an icon on the block diagram based on the conjugation option you choose. By default, this checkbox does not contain a checkmark.
  • pr/pi Type—Specifies the configuration of the real or imaginary pr/pi output terminals.
    • Adapt to source—Specifies whether LabVIEW automatically adjusts the fixed-point configuration of the output data type to avoid overflow and rounding errors. By default, this checkbox contains a checkmark, and LabVIEW dims the following options.
      Note  LabVIEW supports a maximum word length of 64 bits and a maximum integer word length of 1023 bits. If you place a checkmark in this checkbox and the output data type requires a word length that exceeds these maximum values, overflow and/or rounding errors might occur.
    • Signed—Specifies that these terminals are signed.
    • Unsigned—Specifies that these terminals are unsigned.
    • Word length—Specifies the word length of these terminals.
    • Integer word length—Specifies the integer word length of these terminals.
  • Overflow mode—Specifies how this function handles overflow. You can choose either Wrap (default) or Saturate.
    Note  The Saturate option requires more FPGA resources and a longer combinatorial path than the Wrap option does. In this situation, choosing Saturate might decrease the maximum clock rate at which this function can compile.
  • Rounding mode—Specifies how this function rounds the output data if rounding is necessary. You can choose Truncate (default), Round Half-Up, or Round Half-Even. If rounding occurs, the option you choose might affect the amount of resources this function requires.
Implementation DetailsSpecifies options for implementation resources and for pipelining this function internally. These options affect the maximum clock rate at which this function can compile and may exceed available FPGA resources.
  • Resource—Specifies how to implement the multiplier.

    You can choose from the following options:
    • Auto (default)—Specifies that the compiler decides whether to use embedded block multipliers or look-up tables (LUTs) to implement the multiplier.
    • Look-Up Table—Specifies that this function uses LUTs to implement the multiplier.
  • Number of pipelining stages—Specifies how many pipelining stages this function uses internally.

    Increasing the number of stages increases the clock rate at which this function can compile but also increases the latency and the amount of FPGA resources this function requires. The degree of pipelining changes with word length and vector size. The default is Max. Minspecifies a minimal number of pipelining stages.

Block Diagram Inputs

ParameterDescription
xrSpecifies the real part of the x multiplicand.
xiSpecifies the imaginary part of the x multiplicand.
yrSpecifies the real part of the y multiplicand.
yiSpecifies the imaginary part of the y multiplicand.
input validSpecifies whether the next data point has arrived for processing. Wire the output valid output of an upstream node to this input to transfer data from the upstream node to this node.
ready for outputSpecifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the ready for input output of a downstream node to this input of the current node.
Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.

Block Diagram Outputs

ParameterDescription
prReturns the real part of the dot product.
piReturns the imaginary part of the dot product.
operation overflowReturns TRUE if the theoretical computed value exceeds the valid range of the output data type. If operation overflow returns TRUE, the Overflow mode you specify in the configuration dialog box determines the value this function returns.
output validReturns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the input valid input of a downstream node to transfer data from the node to the downstream node.
ready for inputReturns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the ready for output input of an upstream node.
Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the input valid terminal is TRUE during the following cycle.

Linear Algebra Dot Product Details

The real and imaginary inputs of this function must be of the same data type and input pattern, otherwise the data type or array size of the real data in input terminal takes precedent.

The inputs of xr/xi and yr/yi must be both scalar or both 1D fixed-size array. If the interface type of xr/xi and yr/yi differs, the input of xr/xi takes precedent. If both interface types are 1D fixed-size arrays, but the array sizes differ, the input with the smaller array size takes precedent regardless of whether it is xr/xi or yr/yi. If the dominating wire is a 1D fixed-size array, LabVIEW dims Vector size and uses the array size from the wire.

Improving Function Performance by Pipelining

You can improve the timing performance of this function on an FPGA target by adjusting the Number of pipelining stages.

In general, increasing the Number of pipelining stages also increases the maximum clock rate at which this function can compile. However, the actual clock rate depends on many factors, including the following:

  • The FPGA target you use
  • The size of the multiplier
  • The rounding and overflow modes you select
  • The Resource you select
  • Other FPGA logic besides the multiplier

 

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