Owning Palette: Linear Algebra Functions
Requires: FPGA Module
Computes the multiplication of two complex matrices.This function supports only scalar and 1D fixedsize array values of the fixedpoint data type.
Dialog Box Options 
Block Diagram Inputs 
Block Diagram Outputs 
Parameter  Description  

Input Types  Specifies the encodings, word lengths, and integer word lengths of the input terminals of this function.
 
Operation  Specifies whether to conjugate the inputs during operation and specifies the encodings, word lengths, and integer word lengths of the output terminals of this function.
 
Matrix Size  Specifies the dimensions of a given matrix.
 
Interface  Specifies the input and output pattern of matrix A and matrix B and the throughput of the function.
 
Implementation Details  Specifies options for pipelining this function internally. These options affect the maximum clock rate at which this function can compile.

Parameter  Description  

ar  Specifies the real part of the a multiplicand.  
ai  Specifies the imaginary part of the a multiplicand.  
br  Specifies the real part of the b multiplicand.  
bi  Specifies the imaginary part of the b multiplicand.  
a valid  Specifies whether the next data point to a has arrived for processing. Wire the output valid output of an upstream node to this input to transfer data from the upstream node to the a input of this node.  
b valid  Specifies whether the next data point to b has arrived for processing. Wire the output valid output of an upstream node to this input to transfer data from the upstream node to the b input of this node.  
ready for output  Specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the ready for input output of a downstream node to this input of the current node.

Parameter  Description  

cr  Returns the real part of the matrix product of a*b.  
ci  Returns the imaginary part of the matrix product of a*b.  
operation overflow  Returns TRUE if the theoretical computed value exceeds the valid range of the output data type. If operation overflow returns TRUE, the Overflow mode you specify in the configuration dialog box determines the value this function returns.  
output valid  Returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the input valid input of a downstream node to transfer data from the node to the downstream node.  
ready for a  Returns TRUE if this node is ready to accept new input data for the a input. Use a Feedback Node to wire this output to the ready for output input of an upstream node.
 
ready for b  Returns TRUE if this node is ready to accept new input data for the b input. Use a Feedback Node to wire this output to the ready for output input of an upstream node.

Both a valid and b valid are required for matrix A and matrix B since the input cycles of matrix A and matrix B might be different.
The real and imaginary inputs of this function must be of the same data type and input pattern, otherwise the data type or array size of the real portion of the input takes precedent.
You can improve the timing performance of this function on an FPGA target by adjusting the Number of pipelining stages.
In general, increasing the Number of pipelining stages also increases the maximum clock rate at which this function can compile. However, the actual clock rate depends on many factors, including the following: