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Linear Algebra Matrix Multiply Function

LabVIEW 2013 FPGA Module Help

Edition Date: June 2013

Part Number: 371599J-01

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Owning Palette: Linear Algebra Functions

Requires: FPGA Module

Computes the multiplication of two complex matrices.

This function supports only scalar and 1D fixed-size array values of the fixed-point data type.

Details  

Dialog Box Options
Block Diagram Inputs
Block Diagram Outputs

Dialog Box Options

ParameterDescription
Input TypesSpecifies the encodings, word lengths, and integer word lengths of the input terminals of this function.
  • ar/ai Type—Specifies the real or imaginary fixed-point configuration of the ar/ai input terminals.

    If you wire a fixed-point data type to these terminals, LabVIEW dims this section and uses information from the wire.
    • Signed—Specifies that these terminals are signed.
    • Unsigned—Specifies that these terminals are unsigned.
    • Word length—Specifies the word length of these terminals.
    • Integer word length—Specifies the integer word length of these terminals.
  • br/bi Type—Specifies the real or imaginary fixed-point configuration of the br/bi input terminals.

    If you wire a fixed-point data type to these terminals, LabVIEW dims this section and uses information from the wire.
    • Signed—Specifies that these terminals are signed.
    • Unsigned—Specifies that these terminals are unsigned.
    • Word length—Specifies the word length of these terminals.
    • Integer word length—Specifies the integer word length of these terminals.
OperationSpecifies whether to conjugate the inputs during operation and specifies the encodings, word lengths, and integer word lengths of the output terminals of this function.
  • Conjugate A—Specifies whether to conjugate the inputs of matrix A during operation. Selecting this option does not require additional FPGA resources. LabVIEW displays an icon on the block diagram based on the conjugation option you choose. By default, this checkbox does not contain a checkmark.
  • Conjugate B—Specifies whether to conjugate the inputs of matrix B during operation. Selecting this option does not require additional FPGA resources. LabVIEW displays an icon on the block diagram based on the conjugation option you choose. By default, this checkbox does not contain a checkmark.
  • cr/ci Type—Specifies the fixed-point configuration of the real or imaginary cr/ci output terminals.
    • Adapt to source—Specifies whether LabVIEW automatically adjusts the fixed-point configuration of the output data type to avoid overflow and rounding errors. By default, this checkbox contains a checkmark, and LabVIEW dims the following options.
      Note  LabVIEW supports a maximum word length of 64 bits and a maximum integer word length of 1023 bits. If you place a checkmark in this checkbox and the output data type requires a word length that exceeds these maximum values, overflow and/or rounding errors might occur.
    • Signed—Specifies that these terminals are signed.
    • Unsigned—Specifies that these terminals are unsigned.
    • Word length—Specifies the word length of these terminals.
    • Integer word length—Specifies the integer word length of these terminals.
  • Overflow mode—Specifies how this function handles overflow. You can choose either Wrap (default) or Saturate.
    Note  The Saturate option requires more FPGA resources and a longer combinatorial path than the Wrap option does. In this situation, choosing Saturate might decrease the maximum clock rate at which this function can compile.
  • Rounding mode—Specifies how this function rounds the output data if rounding is necessary. You can choose Truncate (default), Round Half-Up, or Round Half-Even. If rounding occurs, the option you choose might affect the amount of resources this function requires.
Matrix SizeSpecifies the dimensions of a given matrix.
  • M—Specifies the row number of inputs for matrix A.
  • L—Specifies the column number of inputs for matrix A and the row number of inputs for matrix B.
  • N—Specifies the column number of inputs for matrix B.
InterfaceSpecifies the input and output pattern of matrix A and matrix B and the throughput of the function.
  • Input pattern of A—Specifies that the function receives data from matrix A element by element in the matrix, by vector, by row-wise, or by column-wise.

    Matrix A and matrix B must both use the same input pattern. If you choose an element input pattern for the Input pattern of A, LabVIEW dims the vector input patterns for the Input pattern of B. If you choose a vector input pattern for the Input pattern of A, LabVIEW dims the element input patterns for the Input pattern of B.
    • Row-Wise Element—Specifies that matrix A receives one element per clock cycle by row of the matrix.
    • Column-Wise Element—Specifies that matrix A receives one element per clock cycle by column of the matrix.
    • Row Vector—Specifies that matrix A receives one vector per clock cycle by row.
    • Column Vector—Specifies that matrix A receives one vector per clock cycle by column.
  • Throughput—Specifies the minimum number of clock cycles between two successive valid input matrices. LabVIEW calculates the Throughput of this function based on the values of M, L, and N as specified in Matrix Size. Selecting fewer cycles per matrix results in a higher throughput rate.
  • Input pattern of B—Specifies that the function receives data from matrix B element by element in the matrix, by vector, by row-wise, or by column-wise.

    Matrix A and matrix B must both use the same input pattern. If you choose an element input pattern for the Input pattern of A, LabVIEW dims the vector input patterns for the Input pattern of B. If you choose a vector input pattern for the Input pattern of A, LabVIEW dims the element input patterns for the Input pattern of B.
    • Row-Wise Element—Specifies that matrix B receives one element per clock cycle by row of the matrix.
    • Column-Wise Element—Specifies that matrix B receives one element per clock cycle by column of the matrix.
    • Row Vector—Specifies that matrix B receives one vector per clock cycle by row.
    • Column Vector—Specifies that matrix B receives one vector per clock cycle by column.
  • Output pattern—Specifies that the function returns data for matrix C element by element in the matrix, by vector, or by row-wise.
    • Row-Wise Element—Specifies that matrix C returns one element per clock cycle by row.
    • Row Vector—Specifies that matrix C returns one vector per clock cycle by row.
    • Column Vector—Specifies that matrix C returns one vector per clock cycle by column.
Implementation DetailsSpecifies options for pipelining this function internally. These options affect the maximum clock rate at which this function can compile.
  • Number of pipelining stages—Specifies how many pipelining stages this function uses internally.

    Increasing the number of stages increases the clock rate at which this function can compile but also increases the latency and the amount of FPGA resources this function requires. The degree of pipelining changes with word length and vector size. The default is Max. Minspecifies a minimal number of pipelining stages.

Block Diagram Inputs

ParameterDescription
arSpecifies the real part of the a multiplicand.
aiSpecifies the imaginary part of the a multiplicand.
brSpecifies the real part of the b multiplicand.
biSpecifies the imaginary part of the b multiplicand.
a validSpecifies whether the next data point to a has arrived for processing. Wire the output valid output of an upstream node to this input to transfer data from the upstream node to the a input of this node.
b validSpecifies whether the next data point to b has arrived for processing. Wire the output valid output of an upstream node to this input to transfer data from the upstream node to the b input of this node.
ready for outputSpecifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the ready for input output of a downstream node to this input of the current node.
Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.

Block Diagram Outputs

ParameterDescription
crReturns the real part of the matrix product of a*b.
ciReturns the imaginary part of the matrix product of a*b.
operation overflowReturns TRUE if the theoretical computed value exceeds the valid range of the output data type. If operation overflow returns TRUE, the Overflow mode you specify in the configuration dialog box determines the value this function returns.
output validReturns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the input valid input of a downstream node to transfer data from the node to the downstream node.
ready for aReturns TRUE if this node is ready to accept new input data for the a input. Use a Feedback Node to wire this output to the ready for output input of an upstream node.
Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to the a input of this node during the following cycle. LabVIEW discards this data even if the a valid terminal is TRUE during the following cycle.
ready for bReturns TRUE if this node is ready to accept new input data for the b input. Use a Feedback Node to wire this output to the ready for output input of an upstream node.
Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to the b input of this node during the following cycle. LabVIEW discards this data even if the b valid terminal is TRUE during the following cycle.

Linear Algebra Matrix Multiply Details

Both a valid and b valid are required for matrix A and matrix B since the input cycles of matrix A and matrix B might be different.

The real and imaginary inputs of this function must be of the same data type and input pattern, otherwise the data type or array size of the real portion of the input takes precedent.

Improving Function Performance by Pipelining

You can improve the timing performance of this function on an FPGA target by adjusting the Number of pipelining stages.

In general, increasing the Number of pipelining stages also increases the maximum clock rate at which this function can compile. However, the actual clock rate depends on many factors, including the following:

  • The FPGA target you use
  • The size of the multiplier
  • The rounding and overflow modes you select
  • Other FPGA logic besides the multiplier

 

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