Owning Palette: Linear Algebra Functions
Requires: FPGA Module
Computes the norm square of a complex vector.This function supports only scalar and 1D fixedsize array values of the fixedpoint data type.
Dialog Box Options 
Block Diagram Inputs 
Block Diagram Outputs 
Parameter  Description  

Input Vector Configuration  Specifies the encodings, word lengths, and integer word lengths of the input terminals of this function.
 
Operation 
 
Implementation Details  Specifies options for implementation resources and for pipelining this function internally. These options affect the maximum clock rate at which this function can compile and may exceed available FPGA resources.

Parameter  Description  

xr  Specifies the real part of the input to this function.  
xi  Specifies the imaginary part of the input to this function.  
input valid  Specifies whether the next data point has arrived for processing. Wire the output valid output of an upstream node to this input to transfer data from the upstream node to this node.  
ready for output  Specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the ready for input output of a downstream node to this input of the current node.

Parameter  Description  

norm square  Returns the norm square of input vector x.  
operation overflow  Returns TRUE if the theoretical computed value exceeds the valid range of the output data type. If operation overflow returns TRUE, the Overflow mode you specify in the configuration dialog box determines the value this function returns.  
output valid  Returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the input valid input of a downstream node to transfer data from the node to the downstream node.  
ready for input  Returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the ready for output input of an upstream node.

The xr/xi inputs of this function must be of the same data type and input pattern, otherwise the data type or array size of the xr input terminal takes precedent. If the dominating wire is a 1D fixedsize array, LabVIEW dims Vector size and uses the array size from the wire.
You can improve the timing performance of this function on an FPGA target by adjusting the Number of pipelining stages.
In general, increasing the Number of pipelining stages also increases the maximum clock rate at which this function can compile. However, the actual clock rate depends on many factors, including the following: