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Creating Triggers and Counters (FPGA Module)

LabVIEW 2013 FPGA Module Help

Edition Date: June 2013

Part Number: 371599J-01

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The FPGA Module includes functions for performing basic I/O. However, you might have applications that require customized I/O functionality. Use the FPGA I/O Node as a building block to create customized I/O applications such as triggers and counters.

Creating Triggers

In many applications, you need to wait for a trigger before performing an action. You can wait for a trigger on a single digital input using the Wait on Rising Edge method with the FPGA I/O Method Node.

Note  The I/O resources available and the associated methods vary by target and configuration. Refer to the specific FPGA target hardware documentation for information about available methods and I/O resources.

The Wait on Rising Edge method waits until a condition you specify is met on the digital input before continuing. Place the FPGA I/O Method Node in the first frame of a sequence structure and place the LabVIEW code for the task in the next frame, as shown in the following block diagram.

You also can create more advanced triggering events from the FPGA I/O Node. For example, you might need an application that triggers only when multiple digital lines match a given condition, as shown in the following block diagram.

You can place an FPGA I/O Node configured with a digital input resource in a single-cycle Timed Loop and exit the single-cycle Timed Loop only when the digital inputs match the trigger pattern. Place the single-cycle Timed Loop in the first frame of a sequence structure, just as you do for the Wait on Rising Edge method in the previous example.

You can implement analog triggers using a While Loop in the same manner. Place an FPGA I/O Node configured with an analog input I/O resource and a Comparison function in a While Loop to trigger when the analog input value meets a programmable condition.

Creating Counters

Counters can range from simple event counters to complex signal measurements with multiple inputs and outputs. You can build a simple event counter with the FPGA I/O Method Node function in a While Loop. For example, you can use the Wait on Rising Edge method to wait for a rising edge to occur on a digital input terminal, as shown in the following block diagram.

When the FPGA I/O Method Node detects an edge, the block diagram increments the counter value and stores the counter value in a shift register on the While Loop. You can use a front panel indicator or local variable to view the counter value.

Note  The I/O resources available and the associated methods vary by target and configuration. Refer to the specific FPGA target hardware documentation for information about available methods and I/O resources.

You also can build more advanced counters from the FPGA I/O functions. For example, an application might require a counter with independent count up, count down, and gate inputs and an output, as shown in the following block diagram.

In the block diagram above, the counter value increments when a rising edge occurs on Count Up, the counter value decrements when a rising edge occurs on Count Down, and Gate prevents count up and count down from changing the counter value when Gate is high. Count Up, Count Down, and Gate are the names of specific digital I/O resources on the FPGA target. The output asserts when the counter value is a multiple of four. You can make simple Boolean decisions in LabVIEW code to determine if the counter counts up, down, or stays the same. You also can make mathematical decisions in LabVIEW code to determine when the output asserts.

You can use the FPGA I/O Method Node to take measurements on input signals, as shown in the following block diagram. For example, you might need to measure the period of an input signal. You can place the FPGA I/O Method Node in the first frame of a sequence structure followed by the Tick Count Express VI in the second frame of the sequence structure. Then place the sequence structure in a While Loop. Wire the current value returned by the Tick Count VI to a shift register to serve as the input for the next iteration of the While Loop. Then subtract the previous time from the current time to determine the period of the input signal.

Tip  Use the single-cycle Timed Loop to increase execution speed and to decrease FPGA usage and jitter in counter applications.

 

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