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Introduction to Cycle-Accurate Simulation (FPGA Module)

LabVIEW 2013 FPGA Module Help

Edition Date: June 2013

Part Number: 371599J-01

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As FPGA designs get larger and more complicated, debugging designs on the FPGA chip becomes less efficient because of the time necessary for compiling and downloading to the target. Along with other debugging techniques, cycle-accurate simulation can help you test the timing behavior of FPGA VI components. Cycle-accurate simulation means that timing is precise but the simulation might not use the exact hardware model to implement it.

Note  Not all targets support cycle-accurate simulation. When the FPGA target supports simulation, you have the option to create a simulation export from the Build Specifications shortcut menu.

Select from the following options for cycle-accurate simulation:

  • Simulate using a test bench that LabVIEW creates—Use this option if you want LabVIEW to create a test bench for you and you have installed QuestaSim or an SE version of ModelSim. You can edit the test bench that LabVIEW creates.
  • Simulate using a test bench that you edit—Use this option if you want to edit a VHDL test bench and you have installed ModelSim, QuestaSim, or Xilinx ISim.

Simulate Using a Test Bench that LabVIEW Creates

To simulate using a test bench that LabVIEW creates, known as co-simulation, create a host VI to debug and test your FPGA VI. Include the Open FPGA VI Reference and Close FPGA VI Reference functions so LabVIEW can interact with the third-party simulator. You must provide simulation models for any IP you include through the CLIP and IP Integration Nodes. You specify the models for CLIP simulation and the IP Integration Node simulation through their configuration wizards. In the following illustration, the combined shaded areas indicate the parts that make up the test bench. LabVIEW generates the test bench template in VHDL. You then can use the LabVIEW host VI to customize interactions with controls, indicators, and other LabVIEW objects. In addition, you can create stimulus and response models for the I/O within the VHDL test bench.

Refer to ni.com for more information about using LabVIEW to interact with a third-party simulator.

Requirements for Co-Simulation

To use co-simulation, you must be familiar with ModelSim and have the following software installed:

  • The Xilinx compilation tools necessary for your hardware configuration. Refer to the FPGA Module installation options on the LabVIEW Platform DVD, or your original media, for more information about installing Xilinx compilation tools for LabVIEW.
  • ModelSim

Simulate Using a VHDL Test Bench That You Edit

To simulate using a VHDL test bench that you edit, known as VHDL-based simulation, you must modify the test bench template that LabVIEW creates to interact with the simulated FPGA VI. In the following illustration, the combined shaded areas indicate the parts that make up the test bench. LabVIEW generates the test bench template in VHDL. You then can edit the host VI portion of the VHDL template to customize interactions with controls, indicators, and other LabVIEW objects. In addition, you can create stimulus and response models for the I/O within the VHDL test bench.

In addition to VHDL code for the FPGA VI, you must provide simulation models for any IP you include through the CLIP and IP Integration Nodes. You specify the models for CLIP simulation and the IP Integration Node simulation through their configuration wizards.

Requirements for VHDL-Based Simulation

To use VHDL-based simulation, you must be familiar with a supported third-party simulator and the VHDL programming language and have the following software installed:

  • The Xilinx compilation tools necessary for your hardware configuration. Refer to the FPGA Module installation options on the LabVIEW Platform DVD, or your original media, for more information about installing Xilinx compilation tools for LabVIEW.
  • One of the following third-party simulators:
    • ModelSim or QuestaSim. Refer to ni.com for more information about supported versions of Mentor Graphics simulators.
    • Xilinx ISim. This software is included with the Xilinx compilation tools.

 

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