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Using LabVIEW Classes when Creating FPGA VIs (FPGA Module)

LabVIEW 2013 FPGA Module Help

Edition Date: June 2013

Part Number: 371599J-01

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You can use certain aspects of LabVIEW object-oriented programming techniques when creating FPGA VIs.

Supported LabVIEW Class Features

  • Class constants, controls, and indicators
  • Class methods
  • Use of all FPGA supported data types within classes
  • Classes contained in the private data of other classes
Note  You cannot use LabVIEW classes on the front panel of a top-level FPGA VI because LabVIEW must be able to resolve all classes at compile time.

Guidelines for Inheritance and Compile-time Resolution of Classes

In LabVIEW object-oriented programming, the type of the object at run time can be the same or a descendant of the type of the wire. When you compile an FPGA VI into a bitfile, data routing is fixed, meaning multiple implementations of code cannot be called dynamically. This restriction means that the compiler must be able to statically determine which type will actually be on the wire at run time. Use the following type guidelines as you create FPGA VIs:

  • You can wire a child wire to a parent class terminal.
  • Compared to any other subVI call, there is no additional overhead with dynamic dispatching in an FPGA VI because the override to invoke is determined at compile time.
  • If an FPGA VI has a LabVIEW class input and is not reentrant, you can call that VI in multiple places in your VI hierarchy and wire it with different wire types at various locations. However, when the compiler analyzes your VI hierarchy, the wire type must resolve to the same class at all locations. This applies to both static dispatch and dynamic dispatch VIs.
  • The execution order of classes wired to local variables must ensure that all executions of the local variable match in data type.
  • All objects in an array must resolve to the same class.
  • Case structure tunnels in all frames must resolve to the same class.
  • The compiler resolves the class for shift registers and Feedback Nodes at the initialization terminal and then uses that type for the rest of the loop. Uninitialized shift registers and Feedback Nodes resolve to the class of the wire. If you introduce a child class within the loop, the compile fails.

The following FPGA VI compiles only if the subVI always returns the same type at its output that appears at its input.


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