The single-precision floating-point (SGL) data type provides more accuracy than a 24-bit fixed-point data type but reduces overall performance due to the increased latency of functions and the large number of FPGA resources that it uses. Evaluate your usage of numeric data types to determine which data type best suits your design.
The following list describes behavior to consider when developing FPGA applications with the single-precision floating-point data type:
Most functions cannot perform single-precision floating-point operations inside a single-cycle Timed Loop because they require more than one clock cycle to execute but they do not have handshaking signals. The following features are supported inside the single-cycle Timed Loop with single-precision floating-point data:
Refer to the FPGA VI below for an example of how to pass single-precision floating-point data to a single-cycle Timed Loop using FIFOs.
The top loop shows data passing through the Square and Add functions outside the single-cycle Timed Loop. The intermediate result is then passed into the single-cycle Timed Loop through a FIFO Method Node to calculate the square root of the data. Finally a DMA FIFO passes the result back to the host computer.
Consider the following uses when designing FPGA applications using single-precision floating-point operations.
Performing I/O conversion to the FPGA frees processing on the host computer, especially in real-time systems. If you have FPGA resources available, perform fixed-point I/O to single-precision floating-point data conversions on the FPGA to free the host processor to perform other operations, such as meeting real-time requirements.
Convert heterogeneous data paths into the SGL data type in order to handle them with common code. This conversion is useful in situations where you want to operate on data from multiple inputs that return different fixed-point data types.
The following FPGA VI shows an NI cRIO-9104 as it acquires data from two modules, converts to the SGL data type, and writes the data to a DMA FIFO.