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Integrating Third-Party IP (FPGA Module)

LabVIEW 2013 FPGA Module Help

Edition Date: June 2013

Part Number: 371599J-01

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You can use two methods to integrate third-party IP into FPGA VIs: the component-level IP (CLIP) interface and the IP Integration Node. This topic compares each method and provides advice on deciding between the methods.

Supported IP File Types

You can use IP defined using:

  • VHDL
  • Verilog
  • Netlist files
  • Xilinx CORE Generator (.xco files)
Note  To import Verilog files or a large file hierarchy, you first need to compile this IP to a netlist file.

Xilinx CORE Generator IP

Xilinx provides and maintains the Xilinx CORE Generator IP. LabVIEW uses the IP Integration Node to incorporate Xilinx CORE Generator IP into an FPGA VI. Because Xilinx may deprecate IP cores from older releases, National Instruments can only guarantee support in the IP Integration Node for .xco files created using the current version of the Xilinx tools for your FPGA target.

Note  Xilinx licenses the Xilinx CORE Generator IP. You can find the licensing information in the Context Help window for a specific Xilinx CORE Generator IP. To import a license, place the .lic file in the C:\NIFPGA\programs\XilinxY_Z\ISE\coregen\core_licenses directory, where XilinxY_Z is the current version of the Xilinx tools for your FPGA target.

National Instruments installs the Xilinx CORE Generator, coregen.exe, in the same directory as LabVIEW.exe. By default, the Xilinx CORE Generator is located in the C:\NIFPGA\programs\XilinxY_Z\ISE\bin\nt directory, where XilinxY_Z is the current version of the Xilinx tools for your FPGA target.

Related Information

Using VHDL Code as Component-Level IP (FPGA Module)

IP Integration Node

Integrating Xilinx CORE Generator IP into FPGA VIs (FPGA Module)

When to Use the CLIP Interface

Use CLIP if:

  • You want to constrain the IP by using a .ucf file
  • The IP accesses FPGA I/O
  • The IP uses clocks in any of the following ways:
    • The IP uses more than two clocks
    • The IP uses two clocks and the FPGA-derived clock executes at a rate that is not an integer multiple of the single-cycle Timed Loop clock
    • The IP uses two clocks and the FPGA-derived clock executes at a rate that is an integer multiple of the single-cycle Timed Loop clock, but the edges and/or phases of the clocks are either independent or not aligned
  • You want to use a clock from the IP as a clock for a single-cycle Timed Loop
  • The IP executes in parallel with LabVIEW block diagram code
  • The IP executes outside a single-cycle Timed Loop
  • You want to declare and use the IP at the project level
Note  You can specify constraints in the CLIP interface using the Xilinx Foundation user-constraint file (.ucf) file format. However, if you apply a constraint to a CLIP signal, the LabVIEW block diagram must use that signal or else LabVIEW returns a Xilinx error when you compile the VI.

When to Use the IP Integration Node

Use the IP Integration Node if:

  • The IP is designed to map one or more ports to the single-precision floating-point data type in LabVIEW
  • The IP is from the Xilinx CORE Generator
    Note  Support for the Xilinx CORE Generator varies by target. Refer to the target hardware documentation for information about Xilinx CORE Generator support.
  • You want to export a .ngc file for simulation but do not have the corresponding .vhd file(s)
  • The top-level synthesis file is a .ngc or .xco file
  • The IP is designed to use at most two clocks: one that is wired to the single-cycle Timed Loop and, optionally, an FPGA-derived clock that executes at a rate that is an integer multiple of the single-cycle Timed Loop clock rate
  • The IP is designed to execute inside a single-cycle Timed Loop
  • You want to declare and use IP at a VI level; for example, in a reentrant VI
  • You want to map a port to a Boolean array data type in LabVIEW

Details

The following table compares the two methods in more detail.

CLIP IP Integration Node
Supported synthesis file formats
Note  Synthesis files of supported file formats are included in the compilation. Synthesis files of unsupported file formats are not included in the compilation, and adding them may cause unexpected behavior.
.vhd, .ngc, .ucf, .xco, .coe, .data, .edn, .edif, .ncd, .vhe, .bmm
Note  You cannot use .ngc or .xco files as top-level synthesis files. You must exclude .ngc files from the simulation model.
.vhd, .ngc, .xco, .coe, .data, .ncd, .vhe, .bmm, .edn, .edif, .edf
Support for simulation

Supported LabVIEW data type
  • Boolean
  • Integer
  • Fixed-point
Note  CLIP sockets for certain FPGA hardware targets support the Boolean array data type. Refer to the target hardware documentation for information about CLIP socket support.
  • Boolean
  • Boolean array
  • Integer
  • Fixed-point
  • Single-precision floating-point
Execution model Executes parallel to, and independent of, the data flow of an FPGA VI Executes as defined by the data flow of an FPGA VI
Place of declaration and behavior Declared in a LabVIEW project; acts as a global Declared locally in an FPGA VI
Supported execution modes
  • Outside single-cycle Timed Loop
  • Inside single-cycle Timed Loop
Inside single-cycle Timed Loop
Support for multiple clock domains Maximum number of clocks defined by FPGA Maximum of two clocks: an SCTL clock and an FPGA-derived clock, where the derived clock executes at a rate that is an integer multiple of the SCTL clock
Support for accessing clocks from the IP as clocks for a single-cycle Timed Loop

Support for VHDL generics

Support for constraints on IP

Support for accessing FPGA I/O


 

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