To decrease the amount of space the FPGA VI uses, reduce the number of front panel controls and indicators on the top-level FPGA VI. Each front panel object in a top-level FPGA VI consumes a significant amount of space on the FPGA because LabVIEW includes additional logic to communicate between the top-level FPGA VI and the host VI. Registers that store front panel control and indicator data require more flip-flops than internal registers.
Front panel objects in subVIs do not communicate directly with the host VI and therefore do not consume additional space on the FPGA. SubVI controls and indicators that must hold state information from one call to another use registers to store data. SubVI controls and indicators that only pass data into and out of a subVI consume no logic resources on the FPGA.
Arrays appearing as top-level front panel objects consume significant space on the FPGA because each bit in the array uses a flip-flop on the FPGA. Consider replacing arrays with FIFOs or memory items to transfer data.
When you wire an array as an input to a function, the FPGA compiler creates the equivalent of a For loop to process each element of the array in sequence. If you wire a cluster as an input to an FPGA VI or function, the FPGA compiler creates parallel logic for each element of the cluster. The relationship between arrays and clusters is recursive such that if you wire a cluster of arrays as an input, the arrays are processed in parallel and the array elements are processed sequentially.
|Note Performing operations on arrays can limit the maximum top-level or derived clock rate. To maximize the FPGA clock rate, process single data points instead of arrays.|
If you do not need to access front panel controls and indicators from a host VI, consider replacing the controls and indicators with global variables to pass data within an FPGA VI. If you do not need to pass data, consider replacing controls with constants to decrease the amount of space the FPGA VI uses.
To reduce resources, use Feedback Nodes instead of controls to store data in subVIs.
To reduce the number of front panel objects, you might be able to combine objects, as shown in the following illustration.
In the illustration above, each Boolean control on the top-level FPGA VI contains extra logic that consumes space on the FPGA. However, if you use a single 8-bit numeric control to represent the data, only one control contains extra logic. You can use the Number To Boolean Array and Index Array functions to access elements of the numeric control.