Optimizing FPGA VIs for Speed and Size (FPGA Module)

LabVIEW 2013 FPGA Module Help

Edition Date: June 2013

Part Number: 371599J-01

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If you want to optimize the performance of an FPGA VI, you might be able to modify the FPGA VI to increase speed, decrease the FPGA logic utilization, or both.

The following table includes techniques you can use to optimize an FPGA VI.

Note  To understand the techniques in this table, you must be familiar with registers.
Optimization Technique FPGA Speed FPGA Size

Reduce combinatorial paths.

Use pipelining when appropriate.

Use single-cycle Timed Loops.

Use parallel operations.

Select Never Arbitrate as an arbitration option.

Use non-reentrant subVIs.

Use reentrant subVIs.

Limit the number of front panel objects, such as arrays.

Use the smallest data type possible.

Limit the size of custom data types.

Avoid large VIs and functions, if possible.

Schedule timing using handshaking signals.

Reduce block memory resource usage by configuring dual port read access if possible.

Choose a block memory implementation for array constants unless you need the advantages of a different type of memory. Block memory does not consume FPGA logic resources and tends to compile at a high clock rate relative to other types of memory.

Remove the implicit enable signal from single-cycle Timed Loops that run independently of other nodes on the block diagram. This strategy is most useful for very large designs.


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