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Reducing Combinatorial Paths in FPGA VIs (FPGA Module)

LabVIEW 2013 FPGA Module Help

Edition Date: June 2013

Part Number: 371599J-01

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Long combinatorial paths take more time to execute and limit the maximum clock rate of the clock domain.

Long combinatorial paths are typically a problem in single-cycle Timed Loops because the logic between the input register and the output register must execute within one period of the clock rate you specify. In the single-cycle Timed Loop, LabVIEW removes registers within and between components, which increases the length of the combinatorial path between registers. If the code in a combinatorial path cannot execute within a clock cycle, LabVIEW returns a timing violation in the Compilation Status window.

Note  Deeply nested Case structures also can cause LabVIEW to return a timing violation in the Compilation Status window.

To reduce the length of a combinatorial path, first simplify the logic as much as possible. Once you have reduced the logic to its simplest form, you can further reduce the length of a combinatorial path by dividing the logic into discrete steps and pipelining your design.

Note  If you are using the High Throughput Math functions in a single-cycle Timed Loop, you can use several methods to reduce the length of the combinatorial path between the functions.

 

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