To execute code using a dataflow model, LabVIEW synchronizes logic on the FPGA. By default, LabVIEW FPGA places a register between logic functions on the block diagram to maximize the propagation time available for each operation to execute.
Propagation delay is the time it takes a signal to travel from one register to the next. The combinatorial path is the collection of logic and wiring that a signal encounters from one register to the next.
Because registers update every clock cycle, the propagation delay must not exceed the clock cycle. Propagation delay consists of two components, logic delay and routing delay. Logic delay, which is a function of the number and type of logic gates the signal traverses, often represents the most significant component of propagation delay. Routing delay, which is a function of the length of the wire path the signal traverses, is generally small, because the FPGA compiler attempts to cluster the components of a combinatorial path as tightly as possible on the FPGA. However, as the FPGA VI approaches the size limits of the FPGA, the physical separation between functions increases, and routing delay can become a significant component of the total propagation delay between two registers. The FPGA compiler returns a timing error if the propagation delay between any two registers exceeds the FPGA clock rate. This timing error is known also as a time constraint or period constraint violation.
|Note The logic delay for a given function varies by target. The routing delay varies each time you compile an FPGA VI.|
The LabVIEW FPGA Module is designed to produce circuits that can run at a clock rate of at least 40 MHz outside the single-cycle Timed Loop. A 40 MHz clock rate corresponds to a 25 nanoseconds clock cycle. To prevent the propagation delay between two registers from exceeding 25 ns, most LabVIEW functions include an output register and thus require a full clock cycle to execute. If the propagation delay between two registers exceeds 25 ns, the FPGA VI cannot compile at the 40 MHz default clock rate.
For example, suppose function A requires a 6 ns logic delay and function B requires a 14 ns logic delay. If you wire functions A and B in sequence without a register between them, the total logic delay is 20 ns, which leaves 5 ns for routing delay if you want the functions to compile at the 40 MHz default clock rate. Depending on how the FPGA compiler routes the wires between the functions, the routing delay might or might not exceed 5 ns, as shown in Scenarios 1 and 2 below.
In Scenario 1, the design meets the timing constraints of a 40 MHz clock. In Scenario 2 the design does not meet the timing constraints of a 40 MHz clock and produces a timing violation error when you try to compile the FPGA VI. In contrast, Scenario 3, below, illustrates a register between the two functions. This register placement results in two separate propagation delays. Each of these separate propagation delays can compile at 40 MHz, even if the routing delay is long.
When a function is not in a single-cycle Timed Loop, the FPGA compiler places registers at regular intervals between the logic levels in a function to break up the logic into portions that can execute at the default FPGA clock rate. When a function that includes internal registers, such as the Memory Method Node, runs on the FPGA, the function takes as many clock cycles to execute as the number of registers in the function.
When you need logic to execute with lower latency at the same clock rate, you can use the single-cycle Timed Loop. When you place a function inside a single-cycle Timed Loop, the compiler does not include an output register for the function, so the single-cycle Timed Loop can execute within one clock cycle. Some functions, such as the Scaled Window or FFT Express VI, take multiple clock cycles even when these functions are located in single-cycle Timed Loops. Use handshaking to schedule the timing of data for these functions.
If the propagation delay within a single-cycle Timed Loop exceeds the clock cycle, the Timing Violation Analysis window tells you which single-cycle Timed Loop failed to meet timing requirements. In some cases, you can reduce the length of a combinatorial path by using Feedback Nodes or shift registers to implement a pipelined design.
|Note If you are using the High Throughput Math functions in a single-cycle Timed Loop, you can add internal registers to reduce the length of the combinatorial path between the functions.|
Every FPGA target contains a limited number of flip-flops. Because registers use flip-flops, the number and type of registers used by an FPGA VI can determine whether the FPGA VI fits on the FPGA target. In general, the number of flip-flops used by a register corresponds to the width of the data type. For example, a Boolean register needs only one flip-flop to store data while an I64 register requires 64 flip-flops to store data.
For most users, the limited number of flip-flops on an FPGA is not a problem. However, if you run into space limitations on the FPGA, you must optimize the FPGA VI for size.