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Using Single-Cycle Timed Loops to Optimize FPGA VIs (FPGA Module)

LabVIEW 2013 FPGA Module Help

Edition Date: June 2013

Part Number: 371599J-01

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LabVIEW automatically optimizes code inside a single-cycle Timed Loop to execute more quickly and consume less space on the FPGA, compared to the same code inside a While Loop. The single-cycle Timed Loop does not include enable chain registers inside the loop, which saves time and space. In the following block diagram, the code within the While Loop takes four clock cycles to execute, excluding the overhead of the While Loop, which takes two additional clock cycles to execute. The red vertical lines indicate where each clock cycle ends inside the While Loop. The same operation in a single-cycle Timed Loop executes within one clock cycle, if the clock period is long enough.

You also can include logic in a single-cycle Timed Loop to optimize code in an FPGA VI, as shown in the following block diagram.

If you use a single-cycle Timed Loop within a While Loop, as shown in the block diagram above, wire a TRUE constant to the condition terminal so that the code within the Timed Loop executes only once.

If you want to use the single-cycle Timed Loop, all operations inside the loop must fit within one cycle of the FPGA clock. Refer to the single-cycle Timed Loop topic for more information about objects you cannot use in a single-cycle Timed Loop.


 

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