LabVIEW uses the base clock properties when setting timing constraints on circuits generated from the FPGA VI during compilation.
Every VI or function you place in an FPGA VI takes a certain amount of time, known as logic delay, to execute. The top-level clock on an FPGA target determines the execution time of the individual functions and VIs on the FPGA VI block diagram. If you change the frequency of the top-level clock, you also change the execution speed of functions on the block diagram and the execution rate of the FPGA VI.
By controlling the execution rate of the FPGA VI, you specify the timing objectives of an FPGA application. Operations occur at the rate determined by the dataflow of the VI if you do not include additional programming. To control or measure the execution timing, use the Timing VIs. You also can use the Timing VIs to create custom I/O applications such as counters and triggers.