Owning Palette: FPGA Interface VIs and Functions
Requires: FPGA Interface
Runs an FPGA VI on a development computer with simulated I/O for the specified number of clock ticks. This node writes all inputs, passes the amount of simulated time you specify, then reads all outputs. The FPGA VI pauses execution until the FPGA Desktop Execution Node is called again, at which point the FPGA VI resumes for the specified number of clock ticks.
|Dialog Box Options|
|Block Diagram Inputs|
|Block Diagram Outputs|
|Simulation Configuration||Contains the following options:|
|Terminal Configuration||Contains the following options:|
|Error In||Describes error conditions that occur before this node runs.|
|Error Out||Contains error information. This output provides standard error out functionality.|
You must configure the target to execute the VI on the desktop computer with simulated I/O. You cannot use this node alongside a custom VI for FPGA I/O.