FPGA Desktop Execution Node

LabVIEW 2013 FPGA Module Help

Edition Date: June 2013

Part Number: 371599J-01

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Owning Palette: FPGA Interface VIs and Functions

Requires: FPGA Interface

Runs an FPGA VI on a development computer with simulated I/O for the specified number of clock ticks. This node writes all inputs, passes the amount of simulated time you specify, then reads all outputs. The FPGA VI pauses execution until the FPGA Desktop Execution Node is called again, at which point the FPGA VI resumes for the specified number of clock ticks.


Dialog Box Options
Block Diagram Inputs
Block Diagram Outputs

Dialog Box Options

Simulation ConfigurationContains the following options:
  • VI—Specifies the FPGA VI to run.
    • Browse VI—Displays the Select VI dialog box. Click this button to select the VI you want to reference.
  • Reference Clock—Specifies an available FPGA clock to use as the timing source for simulated time.
  • Clock Ticks—Specifies the number of clock ticks to run the FPGA VI for each call to the node. You must specify a non-zero integer.
Terminal ConfigurationContains the following options:
  • Available Resources—Displays the I/O resources and front panel controls and indicators available for simulating with the FPGA Desktop Execution Node. The FPGA target you specify in the VI selection box determines the resources that appear in the Available Resources tree.

    Click the Add/Remove buttons to the right of the Available Resources list to add and remove resources.
  • Selected Resources—Displays the list of resources you select from the Available Resources tree.
  • Change Terminal Direction—Contains the following options:
    • In—Specifies that the selected resource has an input terminal on the block diagram.
    • Out—Specifies that the selected resource has an output terminal on the block diagram.
    • In/Out—Specifies that the selected resource has both input and output terminals on the block diagram.

Block Diagram Inputs

Error InDescribes error conditions that occur before this node runs.

Block Diagram Outputs

Error OutContains error information. This output provides standard error out functionality.

FPGA Desktop Execution Node Details

You must configure the target to execute the VI on the desktop computer with simulated I/O. You cannot use this node alongside a custom VI for FPGA I/O.


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