June 2013, 370960K-01
Requires: FPGA Interface. This topic might not match its corresponding palette in LabVIEW depending on your operating system, licensed product(s), and target.
Use the FPGA Interface VIs and functions to communicate with an FPGA VI from a host VI. The VI that runs on an FPGA target is called the FPGA VI. A host VI is a VI that communicates with the FPGA VI to control the FPGA target. A host VI can run on a computer running Windows or on an RT target.
You can use the FPGA Interface functions to programmatically control and communicate with an FPGA VI. Use the FPGA Interface functions to perform the following operations in host VIs:
|Note This palette is available only when you edit a VI under My Computer or an RT target in the Project Explorer window.|
The functions on this palette can return general LabVIEW error codes, specific FPGA Interface error codes, or error codes specific to the FPGA target.
|Close FPGA VI Reference||Closes the reference to the FPGA VI and, optionally, resets execution of the VI. By default, the Close FPGA VI Reference function closes the reference to the FPGA VI and resets the FPGA VI. To configure this function only to close the reference, right-click the function and select Close from the shortcut menu.|
|Dynamic FPGA Interface Cast||Casts Session In to the data type, Type. This function only changes the type of elements that FPGA VI reference contains. This function does not convert data. Use this function with the FPGA Interface Dynamic Refnum constant to create a dynamic host interface. Some FPGA targets might not support this function.|
|FPGA Desktop Execution Node||Runs an FPGA VI on a development computer with simulated I/O for the specified number of clock ticks. This node writes all inputs, passes the amount of simulated time you specify, then reads all outputs. The FPGA VI pauses execution until the FPGA Desktop Execution Node is called again, at which point the FPGA VI resumes for the specified number of clock ticks.|
|FPGA Interface Dynamic Refnum||Use the FPGA Interface Dynamic Refnum constant to specify an FPGA interface. Specify the configuration of the interface by right-clicking the constant and selecting Configure FPGA VI Reference from the shortcut menu.|
|Invoke Method||Invokes an FPGA Interface method or action from a host VI on an FPGA VI. Use methods to do the following: download, abort, reset, and run the FPGA VI on the FPGA target, wait for and acknowledge FPGA VI interrupts, read DMA FIFOs, and write to DMA FIFOs. The methods you can choose from depend on the target hardware and the FPGA VI.
To specify a method, right-click the Invoke Method function and select Method»x from the shortcut menu, where x is the specific method. You must wire the FPGA VI Reference In input to view the available methods in the shortcut menu.
|Open Dynamic Bitfile Reference||Opens a reference to an FPGA bitfile at runtime and returns a dynamic FPGA interface. Use this function in place of the Open FPGA VI Reference function when you want to open a bitfile by path at run time.|
|Open FPGA VI Reference||Opens a reference to the FPGA VI or bitfile and FPGA target you specify. Right-click the Open FPGA VI Reference function and select Configure Open FPGA VI Reference from the shortcut menu to display the Configure Open FPGA VI Reference dialog box.
You must open a reference to the FPGA target before you can communicate between the host VI and the FPGA VI. You can download and run only one FPGA VI at a time on a single FPGA target. If you attempt to download a second VI to the FPGA target while the first FPGA VI is still in use, LabVIEW reports an error and the download fails.
|Read/Write Control||Reads a value from or writes a value to a control or indicator in the FPGA VI on the FPGA target.|
|Advanced Function||This palette includes the Up Cast function.|
|Scaling VIs||Use the Scaling VIs to convert the clock and sample rate for the Loop Timer Express VI and to reconfigure input settings and post-process data from the FPGA Math & Analysis VIs.|
|Simulation VIs||Use the Simulation VIs to interact programmatically with a third-party simulator for cycle-accurate simulation of FPGA applications.|
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