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Version 2013 Features and Changes (FPGA Module)

LabVIEW 2013 FPGA Module Help

Edition Date: June 2013

Part Number: 371599J-01

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Refer to the LabVIEW Features and Changes topic for information about new features in LabVIEW. Refer to the LabVIEW FPGA Module Release and Upgrade Notes for information about upgrade and compatibility issues specific to upgrading from the LabVIEW 2012 FPGA Module to the LabVIEW 2013 FPGA Module. Refer to for information about known issues with the FPGA Module.

The FPGA Module 2013 includes the following new features to help you better manage, implement, and validate your FPGA applications.

Support for Variable-Sized Arrays in FPGA VIs

FPGA VIs now support variable-sized, one-dimensional arrays that resolve to a single size at compile time. Previous versions of the FPGA Module only supported one-dimensional, fixed-size arrays.

Improvements to Debugging and Verification

LabVIEW 2013 brings the following improvements to debugging and verification:

Desktop Execution Node

You now can use the FPGA Desktop Execution Node to debug an FPGA VI. This node runs an FPGA VI on the desktop with simulated I/O for a number of clock ticks that you specify. Use the FPGA Desktop Execution Node to communicate with FPGA resources that you select and to verify your FPGA design.

Support for Sampling Probes

You now can use Sampling probes in FPGA VIs and host VIs to check intermediate values on a wire as a VI runs. The Sampling Probe Watch Window displays the values in a waveform viewer. Use Sampling probes to understand the way signals relate to each other over time.

Updates to Timing Behavior When Executing on a Development Computer with Simulated I/O

Some FPGA resources now use simulated time rather than real time when you execute the VI on a development computer with simulated I/O. Refer to the Introduction to Debugging FPGA VIs on the Host topic for more information about simulated time.

Math and Analysis Functions Improvements: Linear Algebra Functions

You now can use Linear Algebra functions to perform vector and matrix calculations in high speed and high throughput FPGA applications, such as RF applications. The new FPGA Linear Algebra subpalette includes the following functions:

AXI Protocol Exposed on Some Xilinx IP

National Instruments exposes the AXI, or Advanced eXtensible Interface, protocol for certain Xilinx CORE Generator IP on specific hardware targets. Refer to the IP data sheet for information about interface and FPGA device support.

Host Interface Improvements

You now can use the Open Dynamic Bitfile Reference function to reference an FPGA bitfile by path at run time when communicating with an FPGA target.

Improvements to Data Storage and Transfer Functions

LabVIEW 2013 brings the following improvements to the Data Storage and Transfer functions:

Improvements to Data Transfer

You now can use handshake items to achieve lossless data transfer from a writing domain to a reading domain, and to notify the writing domain when the reader receives the data. This method of handshaking data saves development time over manually implementing the four-wire handshaking protocol.

Improvements to Memory Items

You now can store data in one clock domain and access the data from a different clock domain using a memory item implemented with block memory.

Improvements to CLIP Clock Connections

You now can create necessary FPGA target clocks from the Clock Selections page of the Component-Level IP Properties dialog box and link them to certain corresponding CLIP clocks automatically, which saves development time when compared to adding these clocks manually.

Performance Improvements While Executing on the Development Computer

Depending on your memory consumption and performance needs, you now can choose whether to persist memory values between VI executions while executing on the development computer.


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