Preparing IP for Use with the IP Integration Node (FPGA Module)

LabVIEW 2014 FPGA Module Help

Edition Date: June 2014

Part Number: 371599K-01

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The following tables describe recommendations and requirements for using IP with the IP Integration Node.

Recommendations for All IP

The following recommendations apply to all IP you use with the IP Integration Node.

Recommendation Details

Use VHDL. The IP Integration Node is designed to work best with VHDL. Using Verilog limits the available simulation options. To integrate Verilog code, first compile the code into a netlist file. You then can use this file with the IP Integration Node.

Validate the IP outside of LabVIEW. The IP Integration Node is not a debugging or testing environment. Before integrating the IP into the IP Integration Node, National Instruments recommends validating IP by synthesizing it using the Xilinx compilation tools first. You also can create a test bench in a third-party simulation tool to ensure the IP is robust.

Synchronize IP output ports to the rising edge of the single-cycle Timed Loop clock. Synchronizing output ports to the rising edge of the single-cycle Timed Loop clock ensures that simulating the FPGA VI produces the same results as executing the VI on an FPGA target.

Requirements for All IP

The following requirements apply to all IP you use with the IP Integration Node.

Requirement Details

Install the necessary Xilinx compilation tools on the development computer. If you do not install these tools on the development computer, you cannot configure the IP Integration Node, export the FPGA VI for simulation, or execute the FPGA VI on the development computer. You only can execute the FPGA VI on an FPGA when the IP Integration Node was previously configured on a computer that included the Xilinx compilation tools.

Ensure the IP does not contain certain components that are unsupported by the FPGA target on which the IP runs. If the IP contains these types of components, you might not be able to execute the IP on an FPGA.

Ensure the IP has ports and ports are inputs only or outputs only.

Ensure all port names are no longer than 40 characters. If the IP has ports whose names are too long, you have the following options:
  • Rename the port(s).
  • Create a wrapper .vhd file with shorter port names and make this wrapper the top-level synthesis and/or simulation file.

If you plan to simulate the IP, do not include open ports. If you include VHDL code such as port_name => open and try to generate a simulation model, LabVIEW returns an error.

Ensure generics and ports in top-level synthesis and simulation files match. If the top-level synthesis and simulation files are different .vhd files, ensure that all generics and ports declared in one file are declared in the other file. Also, port widths must be identical in both files.

Define at least one entity/architecture pair in the top-level .vhd synthesis and simulation files. The IP Integration Node requires this information to execute and simulate the IP properly. You specify the entity/architecture pairs you want to synthesize/simulate on the Entity, Architecture, and Targets page of the configuration wizard.

Convert the data types ports in the top-level synthesis file to std_logic or std_logic_vector that use downto indexing. The IP Integration Node supports only these data types for ports in top-level synthesis files. The ports must use downto indexing to be consistent with how LabVIEW orders bits. You can write a VHDL wrapper to perform this conversion and then set this wrapper file as the top-level synthesis file. Refer to the support document at for an example of this conversion.
Note  Ports below the top level can be of any data type.

Ensure the IP uses clocks correctly. The IP Integration Node supports IP that uses at most two clocks: the clock you wire to the single-cycle Timed Loop, which can be either an FPGA base clock or FPGA-derived clock, and a secondary derived clock you wire directly to the IP Integration Node. You can derive the secondary clock from either the FPGA base clock or the SCTL clock. The secondary clock must execute at a rate that is an integer multiple (2x, 3x, and so on) of the SCTL clock.
Note  If the IP uses a derived clock, the IP also must use a SCTL clock.

Ensure the IP does not access FPGA I/O. The IP Integration Node does not support IP that attempts to access FPGA I/O. If the IP must access FPGA I/O, use CLIP instead of the IP Integration Node to integrate the IP with the LabVIEW FPGA VI.
Note  Although the IP Integration Node cannot access FPGA I/O directly, you can wire input and output terminals of the IP Integration Node to FPGA I/O Nodes.

Use a clock enable signal if you plan to place the IP inside a Case structure. If you place the IP Integration Node inside a Case structure, you must specify an enable signal. If you do not specify a clock enable signal, LabVIEW returns an error when you attempt to compile the FPGA VI.

Ensure the IP is designed to execute in a single-cycle Timed Loop. You cannot use the IP Integration Node outside a single-cycle Timed Loop.

Verify the paths of any .coe files that a Xilinx IP configuration file includes. These paths must be relative. Any .coe files must be in the same directory as the Xilinx IP configuration file.

Name all IP constants uniquely, and avoid prefixing IP constant names with k.

Recommendations for IP that Contains Sequential Logic

Sequential logic is logic that uses one or more FPGA logic elements, such as flip-flops, to store its state from one clock cycle to the next. Examine the IP to determine whether it contains any sequential logic. If it does, the following recommendations apply to the IP. If the IP does not contain any sequential logic, the IP is combinatorial.

Recommendation Details

Include an enable signal. National Instruments recommends that the IP include a port that maps to an enable signal. If the IP does not include an enable signal, simulating the IP might return different results than when you execute the IP on an FPGA target.

During simulation, the IP executes only when the containing block diagram structure executes. When executing on an FPGA target, the IP always executes regardless of its place on the block diagram or the state of the FPGA VI. This behavior increases the chance that the IP operates on garbage data, including metastable values, when the IP should not be executing at all.

Include both asynchronous and synchronous reset signals. National Instruments recommends you include both asynchronous and synchronous reset signals in the IP to minimize the chances of the IP entering an unknown, and potentially unrecoverable, state. Including an asynchronous reset signal ensures the IP resets simultaneously with other LabVIEW FPGA block diagram objects. Including at least one synchronous reset signal ensures the IP resets properly between consecutive runs of the top-level FPGA VI.
Note  If the IP does not include an enable signal and the FPGA VI resets, LabVIEW might discard the initial values of the IP before the single-cycle Timed Loop can start executing. The lack of an enable signal means nothing prevents the IP from clocking in garbage data while other block diagram functions initialize.

Recommendation for IP that Contains Only Combinatorial Logic

Combinatorial logic is logic that does not store its state, that is, logic that is not sequential. If the IP does not contain any sequential logic, the IP is combinatorial. Complete the following steps if the IP contains only combinatorial logic:

  1. Double-click the IP Integration Node and navigate to the Clock and Enable Signals page.
    Note  If the node is configured already, you can right-click the node and select Configure»Clock and Enable Signals from the shortcut menu.
  2. In the Clock signal name pull-down list, select No clock signal.
  3. Click the OK button to save changes and return to the block diagram.

The IP Integration Node now treats the IP as combinatorial.


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