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The primary means of data storage in a single clock domain using an FPGA application is a memory item.
The LabVIEW FPGA Module has two types of memory items:
|Note If you include multiple reads or writes to the same memory item, the memory item can become a shared resource. To prevent data corruption and jitter, avoid simultaneous read or write requests to a single memory item.|
The following block diagram shows how you can read from and write to a memory item using a Memory Method Node configured for a target-scoped memory item. This VI reads data from memory, increments the data, and then overwrites the same memory location with the new data.
|Note This block diagram is valid only outside the single-cycle Timed Loop. If you use this block diagram within the single-cycle Timed Loop, you must wire at least two Feedback Nodes or two uninitialized shift registers to the Data output of the Read (Memory Method) node because the cycles of read latency of the memory item is set to 2. The x2 under the icon at the top of the Read (Memory Method) node indicates the number of cycles of latency of the memory item.|
Use the Memory Properties dialog box to specify how LabVIEW implements a memory item. Expand the Implementation pull-down menu to display the available memory options, as shown in the following illustration.
|Note Refer to the Memory Properties dialog box topic for help configuring the remaining options in this dialog box.|
Block memory, also known as block random access memory, block RAM, or BRAM, is an internal FPGA resource for data storage. Memory items using block memory compile at a high clock rate relative to other types of memory items. You can configure block memory for read-write access or dual-port read access. You also can use a memory item implemented using block memory to write data in one clock domain and read the data from a different clock domain. In this implementation, you can use only one writer node and one reader node for each memory item. Block memory does not consume FPGA resources. Use block memory first unless you need the advantages of a different type of memory.
|Caution When you use memory items implemented using block memory in multiple clock domains, it is possible to read from and write to the same address simultaneously. However, doing so can result in reading incorrect data.|
A higher number of cycles of read latency results in an increase in internal pipelining, which also can increase the maximum frequency of your compiled design. You can specify the number of cycles of read latency for memory items implemented using block memory on the General page of the Memory Properties dialog box. Refer to the following table to help you determine the number of cycles of read latency for your design.
|Cycles of read latency||Recommendations for Use||Impact on Maximum Frequency|
|0||Available only when implementing memory using look-up tables||No change|
|1||Use this setting if you require valid data quickly, but lack the FPGA resources to use look-up tables||No change|
|2 (default)||Recommended setting for maximum frequency of most designs||Increase|
|3||Use this setting if you need to store a large amount of data
Look-up tables, also known as distributed RAM, consist of logic gates hard-wired on the FPGA. LUTs consume FPGA resources because they can function either as FPGA resources or as memory. Use look-up tables in the following situations:
DRAM is a form of external memory available on some FPGA targets. DRAM provides a large amount of storage space. However, because DRAM is external to the FPGA, the application cannot receive data from DRAM in a single clock cycle. DRAM also requires sequential access, meaning that only one command can access the memory at a time. Sequential access prevents deterministic timing and might increase execution time, depending on how many commands are waiting to access the DRAM.
|Note You cannot implement VI-defined memory items using DRAM.|
When DRAM is available, use it to store large amounts of data that do not fit elsewhere on the FPGA. If DRAM is not available for your target, the Memory Properties dialog box does not list DRAM as an option under the Implementation pull-down menu.