Implementing Multiple Clock Domains (FPGA Module)

LabVIEW 2017 FPGA Module Help

Edition Date: March 2017

Part Number: 371599N-01

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Single-cycle Timed Loops can run under different clock domains. You can specify clock domains in FPGA VIs using the single-cycle Timed Loop. All available FPGA target clocks appear in the Project Explorer window as FPGA target base or derived clocks. You can select any FPGA target base or derived clock that the FPGA target supports as the timing source for a single-cycle Timed Loop. However, the combinatorial path length of the code you place in the single-cycle Timed Loop must be short enough to execute at the clock rate you specify.

Synchronizing I/O Under Different Clock Domains

You might need to transfer data between single-cycle Timed Loops set to run under different clock domains. Digital inputs on most FPGA targets are not synchronized to the top-level FPGA target clock and must be resynchronized. Some FPGA targets allow you to use external clocks or I/O resources specially synchronized to a specific clock. If input data is already synchronous to the top-level FPGA target clock, you can avoid the resynchronization overhead. Refer to the specific FPGA target hardware documentation for information about the synchronicity of available I/O resources.

Transferring Data between Clock Domains

To transfer data between clock domains, you can use single-cycle Timed Loop tunnels, register items, handshake items, local and global variables, or block memory FIFOs. The following table summarizes the characteristics of each method:

Transfer Method FPGA Resource Lossy? Between Parallel Loops? Between Unlimited Domains? Common Use
Single-Cycle Timed Loop Tunnels Logic No No No Datalogging
Register Items and Local and Global Variables Logic Yes Yes Yes Control, Simulation
Memory Items Implemented Using Block Memory Memory Yes Yes No Datalogging
Block Memory FIFOs Logic and Memory No Yes No Datalogging
Handshake Items Logic No Yes No Control, Simulation

Single-Cycle Timed Loop Tunnels

You can use the single-cycle Timed Loop tunnel to wire input and output signals on a single-cycle Timed Loop. LabVIEW handshakes input signals to the loop clock domain. After each iteration of the single-cycle Timed Loop terminates, LabVIEW handshakes any output signals to the top-level FPGA target clock. Single-cycle Timed Loop tunnels maintain the LabVIEW dataflow and therefore cannot be used to transfer data among parallel loops.

Register Items and Local and Global Variables

You can write to a register item or a local or global variable from only one clock domain. You then can read from the register item or local or global variable in as many clock domains as you need. LabVIEW transfers data from the writing domain to the reading domains and uses handshaking to avoid data corruption. You must wait several clock cycles of both the writing and reading domains to handshake a new value. Some values you write from one clock domain might not be read by the destination domain because of the handshaking overhead. To avoid cases where data is written faster than it can be read, you should program additional logic to ensure a two-way communication between the reader and writer, thus preventing data loss.

Note  To ensure that all data written in the same iteration of the sending clock domain arrive together in the destination clock domain, place data in a cluster. The data for each register item or variable handshakes separately.

Memory Items Implemented Using Block Memory

You can use a target-scoped or VI-defined memory item to store data and access it from a different clock domain only if you implement the memory item using block memory. To change the memory implementation, choose Block Memory as the Implementation of the memory item on the General page of the Memory Properties dialog box. In this implementation, you can use only one writer node and one reader node for each memory item.

Caution  When you use memory items implemented using block memory in multiple clock domains, it is possible to read from and write to the same address simultaneously. However, doing so can result in reading incorrect data.

Block Memory FIFOs

You can use a target-scoped or VI-defined FIFO to transfer data between clock domains only if you implement the FIFO using block memory. To change the FIFO implementation, choose Block Memory as the Implementation of the memory item on the General page of the FIFO Properties dialog box. You can write data to a block memory FIFO from only one clock domain. You then can read the FIFO from only one other clock domain.

Note  If you use block memory FIFOs and the clock that the FIFO is using stops, the clock domain receiving the data needs one additional write clock cycle to be aware of the last data point written.

Handshake Items

You can write to a handshake item from only one clock domain. You then can read from the handshake item in the same clock domain or a different clock domain. You can clear the handshake item from any clock domain. LabVIEW uses handshaking to achieve lossless transfer from the writing domain to the reading domain and to notify the writing domain when the reader receives the data. LabVIEW requires several clock cycles of both the writing and reading domains to handshake a new value across clock domains.

Related Information

Creating FPGA-Derived Clocks

Reducing Combinatorial Paths in FPGA VIs

Using Local and Global Variables Carefully

Changing the Top-Level FPGA Target Clock Rate

FIFO Properties Dialog Box

Transferring Data Between Devices or Structures Using FIFOs

Storing Data on an FPGA Target

Memory Properties Dialog Box

FPGA Target Hardware Documentation

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