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By default, CLIP signals use synchronization registers. Each synchronization register adds a delay of a clock cycle before the VHDL code receives the value from the FPGA I/O Node. If the CLIP already includes flip-flops on the signals that go to or from the FPGA VI, you can configure the CLIP signals in LabVIEW to not use synchronization registers. In the Advanced Code Generation page of the FPGA I/O Properties dialog box, set the Number of Synchronizing Registers for Output Data and Number of Synchronizing Registers for Output Enable parameters to 0. If the CLIP runs in the same clock domain as the FPGA VI, you do not need to include flip-flops in the CLIP or synchronization registers in LabVIEW.
When you run the FPGA VI, the FPGA Module compiles the FPGA VI and all instantiated CLIP into the FPGA bitstream.
Refer to the CLIP Tutorial, Part 4: Passing Data between CLIP and VIs for an example of passing data between CLIP and VIs.