Write (FIFO Method)

LabVIEW 2018 FPGA Module Help


Edition Date: March 2018
Part Number: 371599P-01
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Requires: FPGA Module

Writes an element or elements to an FPGA FIFO. Configure the number of elements per write from the Interfaces page of the FIFO Properties dialog box.

Use the FIFO Method Node to implement this method.

The inputs and outputs available for this method depend on if you select the timeout or handshaking interface.

Details  

FIFO In specifies the FIFO. You can wire a FIFO control, FIFO constant, VI-Defined FIFO Configuration node, or the FIFO Out terminal of another FIFO Method Node to FIFO In.
Element specifies the data element or elements you want to store in the FIFO. The Element data type is the data type you configure in the FIFO Properties dialog box when you create the FIFO.
Timeout specifies the time, in number of clock ticks, that the method waits for available space in the FIFO if the FIFO is full. A value of –1 prevents the function from timing out. A value of 0 indicates no wait. Wire a constant of 0 to Timeout if you use the FIFO Method Node in a single-cycle Timed Loop.

This input is the default for the Write method. To display this input, right-click the Write method and select Interface»Timeout from the shortcut menu.
FIFO Out returns FIFO In if FIFO In is wired. Otherwise, FIFO Out returns the FIFO that you specify in the FIFO Method Node.
Timed Out? returns TRUE if space in the FIFO is not available before the function completes execution. If Timed Out? is TRUE, the function does not write Element to the FIFO.
Note  (Xilinx Vivado) In simulation mode, if the FIFO is implemented with the built-in control logic, the Timed Out? value might not reflect the actual behavior on hardware because this method uses Actual Number of Elements in the General Page of the FIFO Properties dialog box as the FIFO depth, which might be smaller than the actual number of elements in the FIFO.
This output is the default for the Write method. To display this output, right-click the Write method and select Interface»Timeout from the shortcut menu.
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

To display this handshaking terminal, right-click the Write method within a single-cycle Timed Loop and select Interface»Handshaking from the shortcut menu.
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

To display this handshaking terminal, right-click the Write method within a single-cycle Timed Loop and select Interface»Handshaking from the shortcut menu.

Write (FIFO Method) Details

If you use this method in a single-cycle Timed Loop, you must set the Write option on the Interfaces page of the FIFO Properties dialog box to Arbitrate if Multiple Requestors Only or Never Arbitrate. When you set the Write option to Arbitrate if Multiple Requestors Only, you cannot use multiple FIFO Method Nodes configured with the Write method to access the same FIFO in the FPGA VI.

If you enable the timeout interface for this method within a single-cycle Timed Loop, you also must wire a constant of 0 to Timeout. If there is no data to write, the method executes and returns a timeout instead of valid data. The method continues to return a timeout until data is available to write.

You can use the handshaking interface only within a single-cycle Timed Loop. Additionally, some targets do not support the handshaking interface for peer-to-peer and DMA FIFOs. LabVIEW returns a compile time error for FIFOs that do not support the handshaking interface.

You can use FIFOs to transfer data among multiple clock domains.

Related Information

Understanding Arbitration Options

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