Scaled Window Express VI

LabVIEW 2018 FPGA Module Help


Edition Date: March 2018
Part Number: 371599P-01
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Owning Palette: FPGA Math & Analysis VIs and Functions

Requires: FPGA Module

Minimizes spectral leakage associated with truncated waveforms. This Express VI scales the windowed time-domain signal so that when a LabVIEW object computes the power or amplitude spectrum of the windowed waveform, all windows provide the same level within the accuracy constraints of the output wavelength.

Use this Express VI before you use the FFT Express VI.
Dialog Box Options
Block Diagram Inputs
Block Diagram Outputs

Dialog Box Options

ParameterDescription
Window ConfigurationContains the following options:
  • Type—Specifies the type of window. You can select from the following options:
    • Hanning
    • Hamming
    • Blackman-Harris
    • Exact Blackman
    • Blackman
    • Flat Top
    • 4 Term B-Harris
    • 7 Term B-Harris
    • Low Sidelobe
  • Length—Specifies the length of the window. The range of Length is [2, 8192].
Output Data TypeContains the following options:
  • Adapt to source—Specifies whether this Express VI decides the output data type. Disable the Adapt to source checkbox if you want to use Word length to determine the output data type.
  • Word length—Specifies any output word length in the range of [1, 32]. Word length is available only if you disable the Adapt to source checkbox.
  • Integer word length—Indicates the output integer word length that this Express VI calculates.
ImplementationContains the following options:
  • Show coefficient index terminal—Specifies whether you specify the indices of the window coefficients in coefficient index. If you do not enable this checkbox, this Express VI automatically indexes the window coefficients.
  • Show reset terminal—Specifies whether this Express VI includes a reset input on the block diagram to reset this Express VI at run time. You can save resources on the FPGA if you do not enable the Show reset terminal checkbox.
Window CoefficientsDisplays the values of the window coefficients.
Execution ModeContains the following options:
  • Outside single-cycle Timed Loop—Specifies that this Express VI runs outside the single-cycle Timed Loop.
  • Inside single-cycle Timed Loop—Specifies that this Express VI runs inside the single-cycle Timed Loop. Selecting Inside single-cycle Timed Loop makes the handshaking signals available for use. Refer to the Scheduling Timing Using Handshaking Signals topic for information about using the handshaking signals available for this Express VI.
  • Clock rate—Specifies the level of pipelining stages this Express VI uses internally. Increasing the number of stages increases the clock rate at which this Express VI can compile for both Inside the single-cycle Timed Loop and Outside the single-cycle Timed Loop. This option does not set the clock rate explicitly.
    Note  Adjusting the value of Clock rate increases the FPGA resource usage and latency of this Express VI. An increased latency indicates that this Express VI takes longer to return a valid result.
  • Throughput—Displays the number of cycles between two successive values of valid input data. This number always is one cycle. Therefore, LabVIEW sets the value according to where you place this Express VI.

    If you select Inside single-cycle Timed Loop, LabVIEW sets the throughput to 1 cycle / sample. If you select Outside single-cycle Timed Loop, LabVIEW sets the throughput to 1 call / sample.
  • Latency—Displays the number of clock cycles this Express VI needs to return a valid result inside a single-cycle Timed Loop. This option is available only if you select Inside single-cycle Timed Loop.

    If you select Outside single-cycle Timed Loop, this Express VI returns valid output data on every call to the Express VI. The Configuration Feedback section displays the number of clock cycles each call takes to execute.
Configuration FeedbackDisplays information about how this Express VI executes. This information is based on the configuration options you specify. LabVIEW displays this information only if you select Outside single-cycle Timed Loop.

Block Diagram Inputs

ParameterDescription
resetSpecifies whether to reset the auto-indexing process. Inside the single-cycle Timed Loop, reset ignores the incoming data point during the reset cycle. reset is available only if you enable the Show reset terminal checkbox in the configuration dialog box.
real data inSpecifies the real part of the input signal.
imaginary data inSpecifies the imaginary part of the input signal. Leave imaginary data in unwired to read only real data.
coefficient indexSpecifies the window coefficient index. coefficient index is available only if you enable the Show coefficient index checkbox in the configuration dialog box.
input validSpecifies whether the next data point has arrived for processing. Wire output valid of an upstream node to input valid to transfer data from the upstream node to this Express VI.

To display this handshaking terminal, select Inside single-cycle Timed Loop in the configuration dialog box.
ready for outputSpecifies whether downstream nodes are ready for this Express VI to return a new value. The default is TRUE. Use a Feedback Node to wire ready for input of a downstream node to ready for output of the current node.
Note  If ready for output is FALSE during a given cycle, output valid returns FALSE during that cycle.
To display ready for output, select Inside single-cycle Timed Loop in the configuration dialog box.

Block Diagram Outputs

ParameterDescription
data indexIndicates the current window coefficient index corresponding to the current output. When running this Express VI inside the single-cycle Timed Loop, LabVIEW ignores this value if output valid is FALSE. You can use data index for debugging.
real data outReturns the real part of the windowed signal.
imaginary data outReturns the imaginary part of the windowed signal.
output validReturns TRUE if this Express VI has computed a result that downstream nodes can use. Use output valid for handshaking with other FPGA VIs and functions.

To display output valid, select Inside single-cycle Timed Loop in the configuration dialog box.
ready for inputReturns TRUE if this Express VI is ready to accept new input data. Use a Feedback Node to wire ready for input to ready for output of an upstream node.
Note  If ready for input returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this Express VI during the following cycle. LabVIEW discards this data even if input valid is TRUE during the following cycle.
To display ready for input, select Inside single-cycle Timed Loop in the configuration dialog box.

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