From 09:00 PM Friday, August 7 - 10:30 AM CST Saturday, August 8, ni.com will be undergoing system upgrades that may result in temporary service interruption.

We appreciate your patience as we improve our online experience.

High Throughput Add Function

LabVIEW 2018 FPGA Module Help


Edition Date: March 2018
Part Number: 371599P-01
View Product Info

DOWNLOAD (Windows Only)


LabVIEW 2016 FPGA Module Help
LabVIEW 2017 FPGA Module Help
LabVIEW 2018 FPGA Module Help
LabVIEW 2019 FPGA Module Help
LabVIEW 2020 FPGA Module Help

Owning Palette: High Throughput Math Functions

Requires: FPGA Module

Computes the sum of x and y.

This function supports only scalar and array values of the fixed-point data type.

Examples

Dialog Box Options
Block Diagram Inputs
Block Diagram Outputs

Dialog Box Options

ParameterDescription
Fixed-Point ConfigurationSpecifies the encodings, word lengths, and integer word lengths of the input and output terminals of this function. The configurations you specify determine the value range of the terminals.
  • x Type—Specifies the fixed-point configuration of the x input terminal.

    If you wire a fixed-point data type to this terminal, LabVIEW dims this section and uses information from the wire.
    • Signed—Specifies that this terminal is signed.
    • Unsigned—Specifies that this terminal is unsigned.
    • Word length—Specifies the word length of this terminal.
    • Integer word length—Specifies the integer word length of this terminal.
  • y Type—Specifies the fixed-point configuration of the y input terminal.

    If you wire a fixed-point data type to this terminal, LabVIEW dims this section and uses information from the wire.
    • Signed—Specifies that this terminal is signed.
    • Unsigned—Specifies that this terminal is unsigned.
    • Word length—Specifies the word length of this terminal.
    • Integer word length—Specifies the integer word length of this terminal.
  • x+y Type—Specifies the fixed-point configuration of the x+y output terminal.
    • Adapt to source—Specifies whether LabVIEW automatically adjusts the fixed-point configuration of the output data type to avoid overflow and rounding errors. By default, this checkbox contains a checkmark and LabVIEW dims the following options.
      Note  LabVIEW supports a maximum word length of 64 bits and a maximum integer word length of 2047 bits. If you place a checkmark in this checkbox and the output data type requires a word length that exceeds these maximum values, overflow and/or rounding errors might occur.
    • Signed—Specifies that this terminal is signed.
    • Unsigned—Specifies that this terminal is unsigned.
    • Word length—Specifies the word length of this terminal.
    • Integer word length—Specifies the integer word length of this terminal.
    • Include overflow status—Specifies whether the output terminal includes the overflow status. LabVIEW propagates this status to downstream nodes. Including this status requires additional FPGA resources. By default, this checkbox does not contain a checkmark.

      If you place a checkmark in this checkbox, the overflow status becomes TRUE in either of the following situations:
      • The overflow status of an input terminal is TRUE.
      • Overflow occurs during the operation of this function.


      If you place a checkmark in the Adapt to source checkbox, LabVIEW sets Include overflow status depending on whether an input terminal includes this status.
  • Overflow mode—Specifies how this function handles overflow. You can choose either Wrap (default) or Saturate.
    Note  The Saturate option requires more FPGA resources and a longer combinatorial path than the Wrap option does. In this situation, choosing Saturate might decrease the maximum clock rate at which this function can compile.
  • Rounding mode—Specifies how this function rounds the output data if rounding is necessary. You can choose Truncate (default), Round Half-Up, or Round Half-Even. If rounding occurs, the option you choose might affect the amount of resources this function requires.
Execution ModeSpecifies how this function executes.
  • Outside single-cycle Timed Loop—Configures this Express VI to execute outside a single-cycle Timed Loop.

    If you select this option and place this Express VI inside a single-cycle Timed Loop, the Code Generation Errors window reports an error when you compile the FPGA VI.
  • Inside single-cycle Timed Loop—Configures this Express VI to execute inside a single-cycle Timed Loop.

    If you select this option and place this Express VI outside a single-cycle Timed Loop, the Code Generation Errors window reports an error when you compile the FPGA VI.
  • Throughput—Displays the number of cycles between two successive values of valid input data. This number always is one cycle. Therefore, LabVIEW sets the value according to where you place this Express VI.

    If you select Inside single-cycle Timed Loop, LabVIEW sets the throughput to 1 cycle / sample. If you select Outside single-cycle Timed Loop, LabVIEW sets the throughput to 1 call / sample.
RegistersSpecifies whether to add internal registers for the function output terminal. This section is available only if you select Inside single-cycle Timed Loop.
Note  Adding registers can reduce the length of the combinatorial path, which can prevent compilation errors that result from a long combinatorial path. However, adding registers also increases the latency of this function, which means this function takes an additional clock cycle to return a valid result.
  • Register outputs—Adds internal registers before the outputs of this function. Selecting this option increases the latency of the function by one cycle.
Optional TerminalSpecifies a setting for displaying an optional block diagram terminal.
  • Operation overflow—Specifies that this function displays the operation overflow output terminal on the block diagram. This terminal indicates whether overflow occurred during the operation of this function.
Configuration FeedbackDisplays information about how this function executes. This information is based on the configuration options you specify.

Block Diagram Inputs

ParameterDescription
xSpecifies an addend.
ySpecifies an addend.
input validSpecifies whether the next data point has arrived for processing. Wire the output valid output of an upstream node to this input to transfer data from the upstream node to this node.

To display this handshaking terminal, select the Inside single-cycle Timed Loop option and place a checkmark in the Register outputs checkbox. These options are located in the configuration dialog box.
ready for outputSpecifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the ready for input output of a downstream node to this input of the current node.
Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
To display this terminal, select the Inside single-cycle Timed Loop option and place a checkmark in the Register outputs checkbox. These options are located in the configuration dialog box.

Block Diagram Outputs

ParameterDescription
x+yReturns the sum of x and y.
operation overflowReturns TRUE if the theoretical computed value exceeds the valid range of the output data type. If operation overflow returns TRUE, the Overflow mode option determines the value this function returns.

LabVIEW displays the operation overflow terminal only if you place a checkmark in the Operation overflow checkbox. This checkbox is located in the Optional Terminal section of the configuration dialog box.
output validReturns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the input valid input of a downstream node to transfer data from the node to the downstream node.

To display this terminal, select the Inside single-cycle Timed Loop option and place a checkmark in the Register outputs checkbox. These options are located in the configuration dialog box.
ready for inputReturns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the ready for output input of an upstream node.
Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the input valid terminal is TRUE during the following cycle.
To display this terminal, select the Inside single-cycle Timed Loop option and place a checkmark in the Register outputs checkbox. These options are located in the configuration dialog box.

Examples

Refer to the following VIs for examples of using the High Throughput Add function:

  • labview\examples\CompactRIO\FPGA Fundamentals\FPGA Math and Analysis\High-Throughput Math\Vector Normalization\Vector Normalization.lvproj
  • labview\examples\R Series\FPGA Fundamentals\FPGA Math and Analysis\High-Throughput Math\Vector Normalization\Vector Normalization.lvproj

WAS THIS ARTICLE HELPFUL?

Not Helpful