FPGA I/O Method Node

LabVIEW 2018 FPGA Module Help

Edition Date: March 2018
Part Number: 371599P-01
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	FPGA I/O In is an optional input that allows you to specify the FPGA I/O item to read or write using an FPGA I/O control or constant. To use an FPGA I/O control as a connector pane input, the FPGA VI must be configured for reentrant execution.
	FPGA I/O Out returns the FPGA I/O item on which you configure the node to operate.

FPGA I/O Method Node Details

Support for certain methods inside and outside the single-cycle Timed Loop varies by target and I/O item. Refer to the specific FPGA target hardware documentation for more information.

Tip  Right-click the FPGA I/O Method Node and select Find Item in Project from the shortcut menu to highlight the I/O item in the Project Explorer window.

Additional parameters vary depending on the related method. Method support varies by FPGA target and I/O resource. Some FPGA targets do not support any methods. A method can have zero or more parameters.

FPGA targets with bidirectional digital I/O lines and ports typically support the following methods for bidirectional I/O items.

• Set Output Data Method—Writes data to the digital line or port without enabling the line or port. You can use the Set Output Data method to optimize performance when performing successive writes to a DIO resource. The data type of the Data input depends on the I/O item. For example, if the I/O item is a digital line, Data requires a Boolean data type.
• Set Output Enable Method—Determines whether the digital input and output resource reads external input or writes output. Wiring TRUE to Set Output Enable for a digital line allows the resource to write data. Wiring FALSE to Set Output Enable allows the resource to read external data. The data type of the Enable input depends on the I/O item. For example, if the I/O item is a digital line, Enable requires a Boolean data type, and if the I/O item is an 8-bit digital port, Enable requires a U8 data type. The binary values of the U8 input correspond to the individual lines of the digital port. Zeros correspond to false inputs and ones correspond to true inputs.
• Get Timed Input Data Method—Reads data from the external digital line. Valid returns TRUE when you configure the DIO resource to read external input by using the Set Timed Output Enable method or after you reset the block diagram. You can use this method to perform successive read operations from a DIO resource on FPGA targets. Data supports the Boolean data type only.
• Set Timed Output Data Method—Writes data to the digital line without enabling the line. Ready returns TRUE when you configure the DIO resource to write output. You can use this method to perform successive write operations to a DIO resource on FPGA targets. Data supports the Boolean data type only.
• Set Timed Output Enable Method—Determines whether the DIO resource reads external input or writes output. Settled returns TRUE when the line I/O direction changes. When you use this method in a single-cycle Timed Loop, the number of clock cycles between the time when you change the Enable value and the time when the Settled value changes to TRUE varies depending on the FPGA target. Set Enable to TRUE for a digital line allows the resource to write data. Set Enable to FALSE allows the resource to read external data. NI recommends that you use this method to configure a DIO resource on FPGA targets when possible. Enable supports the Boolean data type only. When you use this method outside a single-cycle Timed Loop, Settled always returns TRUE.

Error Handling Details

You can right-click the FPGA I/O Method Node on the block diagram and select Show Error Terminals from the shortcut menu to add standard LabVIEW error in and error out parameters to the function. You can use the error terminals to place this node in the data flow of the VI as well as to ensure the data you receive is valid. FPGA targets might report errors differently. Refer to the specific FPGA target hardware documentation for information about how specific FPGA targets report errors.

Note  Adding error in and error out parameters may increase the amount of space the function uses on the FPGA target. The error in and error out parameters also may cause slower execution on the FPGA target.