Transferring Data Using the NI Scan Engine and Variables (FPGA Module)

LabVIEW 2018 FPGA Module Help

Edition Date: March 2018
Part Number: 371599P-01
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If you use programmatic front panel communication to transfer coherent sets of FPGA I/O data to an RT host VI, you must create block diagram code that synchronizes the FPGA VI with the host VI. If the FPGA target supports the NI Scan Engine, you can use the NI Scan Engine to synchronize this data transfer. You then can use user-defined I/O variables to transfer data between the FPGA VI and the RT host VI.

Note  An I/O variable is a type of shared variable that uses the NI Scan Engine for single-point access to I/O data. Refer to the specific FPGA target hardware documentation for information about support for the NI Scan Engine.

Using the NI Scan Engine reduces the amount of code you have to create to access and transfer coherent sets of data between FPGA I/O channels and the RT host VI. With user-defined I/O variables, you can process data on the FPGA target before sending that data to the RT host VI and after sending that data back to the FPGA VI. For example, you can create an application that executes the following steps:

  1. Acquires analog I/O data and performs an FFT on the data in an FPGA VI
  2. Transfers the processed data to a control loop in an RT VI
  3. Transfers output data from the RT control loop back to the FPGA for output to the physical I/O channel

Steps 2 and 3 involve user-defined I/O variables to transfer data between the FPGA VI and RT VI.

(CompactRIO) Refer to the User-Defined IO Variable - Basic.lvproj in the labview\examples\CompactRIO\NI Scan Engine\Getting Started\User-Defined IO Variable - Basic\ directory for an example of using user-defined I/O variables.

Creating User-Defined I/O Variables

Right-click the chassis item in the Project Explorer window and select New»User-Defined Variable from the shortcut menu to create a new I/O variable. Because all I/O variables are unidirectional, you must configure the direction of each user-defined I/O variable as either FPGA to Host or Host to FPGA.

I/O variables that you create this way appear in a container labeled User-defined Variables.

Note  A chassis item can include only one user-defined I/O variable container. However, a user-defined I/O variable container can contain multiple user-defined I/O variables.

Caveats of User-Defined I/O Variables

Be aware of the following caveats when creating and using user-defined I/O variables:

  • You must open a reference to an FPGA VI before using user-defined I/O variables.
  • You can use user-defined I/O variables only on FPGA targets that support the NI Scan Engine. Refer to the target hardware documentation for information about support for the NI Scan Engine.
  • User-defined I/O variables support scanned access only. You cannot use direct access for user-defined I/O variables.
  • If you add a user-defined I/O variable node to the block diagram of an FPGA VI, you must set the execution mode of that FPGA VI to FPGA target. To change the execution mode of an FPGA VI, right-click the chassis item that contains that VI and select Select Execution Mode»FPGA Target. If you select Simulation (Simulated I/O) or Simulation (Real I/O) and that FPGA VI contains a user-defined I/O variable, the Run button appears broken and the FPGA VI cannot run.
  • You can use user-defined I/O variables to communicate between only FPGA VIs and RT VIs running on the same chassis. However, if network publishing is enabled on a user-defined I/O variable, you can use the variable in any RT VI or Windows-based VI within the same LabVIEW project. For example, you can use network-published I/O variables to create a user interface VI that runs on Windows.

Accessing Timing Information from the NI Scan Engine

User-defined I/O variables rely on timing information from the NI Scan Engine. You can access this timing information by adding the Scan Clock I/O item to the block diagram of the FPGA VI. This I/O item transmits timing information, such as the number of FPGA clock cycles during which the signal is high, from the Scan Engine to the FPGA VI. Use this timing information to design an application that guarantees coherency of the data sets you transfer between the FPGA VI and the RT host VI.

Not all chassis support the Scan Clock I/O item. If you are using a chassis that does support this item, the item is located in the Project Explorer window under the Chassis I/O item for the FPGA Target. The following figure shows the location of this item.

Related Information

Using the NI Scan Engine (Real Time, Windows)

Using I/O Variables (Real Time, Windows)

Point-by-Point Analysis and Array-Based Analysis in LabVIEW

FPGA Target Hardware Documentation

Opening a Reference to an FPGA VI, Build Specification, or Bitfile (FPGA Interface)

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