How DMA Transfers Work (FPGA Module)

LabVIEW 2018 FPGA Module Help


Edition Date: March 2018
Part Number: 371599P-01
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A DMA channel consists of two FIFO buffers: one on the host computer and one on the FPGA target. After creating a DMA FIFO, you write block diagram code to write data to, and read data from, the appropriate buffer. For example, if you are transferring data from the FPGA to the host, you write code on the FPGA that writes data to the buffer. You also write code on the host that reads data from the buffer.

Note  DMA communication is unidirectional. To transfer data from the host computer to the FPGA target, you must create additional FIFOs and use another DMA channel.

Because DMA communication is based on FIFOs, data transfer occurs one element at a time. The first element in one buffer is the first element transferred to the other buffer. The following illustration shows an example of this data transfer.

In the previous illustration, the FPGA VI acquires data and writes one element of data to the FPGA buffer of the DMA FIFO. The host VI reads four elements at a time from the host buffer.

Note  Setting buffer sizes appropriately is one best practice to follow when designing applications that use DMA communication.

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